[HTML][HTML] A survey on FPGA-based sensor systems: towards intelligent and reconfigurable low-power sensors for computer vision, control and signal processing
The current trend in the evolution of sensor systems seeks ways to provide more accuracy
and resolution, while at the same time decreasing the size and power consumption. The use …
and resolution, while at the same time decreasing the size and power consumption. The use …
[HTML][HTML] Field programmable gate array applications—A scientometric review
Field Programmable Gate Array (FPGA) is a general purpose programmable logic device
that can be configured by a customer after manufacturing to perform from a simple logic gate …
that can be configured by a customer after manufacturing to perform from a simple logic gate …
A 0.5-V real-time computational CMOS image sensor with programmable kernel for feature extraction
TH Hsu, YR Chen, RS Liu, CC Lo… - IEEE Journal of Solid …, 2020 - ieeexplore.ieee.org
As the growing demand on artificial intelligence (AI) Internet-of-Things (IoT) devices, smart
vision sensors with energy-efficient computing capability are required. This article presents a …
vision sensors with energy-efficient computing capability are required. This article presents a …
A 1000 fps vision chip based on a dynamically reconfigurable hybrid architecture comprising a PE array processor and self-organizing map neural network
This paper proposes a vision chip hybrid architecture with dynamically reconfigurable
processing element (PE) array processor and self-organizing map (SOM) neural network. It …
processing element (PE) array processor and self-organizing map (SOM) neural network. It …
A 5500-frames/s 85-gops/w 3-d stacked bsi vision chip based on parallel in-focal-plane acquisition and processing
L Millet, S Chevobbe, C Andriamisaina… - IEEE Journal of Solid …, 2019 - ieeexplore.ieee.org
This paper presents a 3-D stacked vision chip featuring in-focal-plane read-out tightly
coupled with flexible computing architecture for configurable high-speed image analysis …
coupled with flexible computing architecture for configurable high-speed image analysis …
A programmable vision chip based on multiple levels of parallel processors
W Zhang, Q Fu, NJ Wu - IEEE Journal of Solid-State Circuits, 2011 - ieeexplore.ieee.org
This paper proposes a novel programmable vision chip based on multiple levels of parallel
processors. The chip integrates CMOS image sensor, multiple-levels of SIMD parallel …
processors. The chip integrates CMOS image sensor, multiple-levels of SIMD parallel …
A 1500 fps Highly Sensitive 256256 CMOS Imaging Sensor With In-Pixel Calibration
High-speed CMOS imaging sensors (CIS) normally have low sensitivity because of the large
integration capacitance. They also have high noise because pixel circuits cannot implement …
integration capacitance. They also have high noise because pixel circuits cannot implement …
HDR-ARtiSt: an adaptive real-time smart camera for high dynamic range imaging
This paper describes a complete FPGA-based smart camera architecture named HDR-
ARtiSt (High Dynamic Range Adaptive Real-time Smart camera) which produces a real-time …
ARtiSt (High Dynamic Range Adaptive Real-time Smart camera) which produces a real-time …
A 1/2.5 inch VGA 400 fps CMOS image sensor with high sensitivity for machine vision
Machine vision requires CMOS image sensors (CISs) with high frame rate, short exposure
time, and fine spatial resolution. Recently, capacitive transimpedance amplifier (CTIA) is …
time, and fine spatial resolution. Recently, capacitive transimpedance amplifier (CTIA) is …
A 64 64 Pixels UWB Wireless Temporal-Difference Digital Image Sensor
S Chen, W Tang, X Zhang… - IEEE transactions on very …, 2011 - ieeexplore.ieee.org
In this paper we present a low power temporal-difference image sensor with wireless
communication capability designed specifically for imaging sensor networks. The event …
communication capability designed specifically for imaging sensor networks. The event …