Shadow: Preventing row hammer in dram with intra-subarray row shuffling
As Row Hammer (RH) attacks have been a critical threat to computer systems, numerous
hardware-based (HWbased) RH mitigation strategies have been proposed. However, the …
hardware-based (HWbased) RH mitigation strategies have been proposed. However, the …
Mithril: Cooperative row hammer protection on commodity dram leveraging managed refresh
Since its public introduction in the mid-2010s, the Row Hammer (RH) phenomenon has
drawn significant attention from the research community due to its security implications …
drawn significant attention from the research community due to its security implications …
30-Gb/s 1.11-pJ/bit single-ended PAM-3 transceiver for high-speed memory links
A 30-Gb/s three-level pulse amplitude modulation (PAM-3) transceiver is designed with a
one-tap tri-level decision feedback equalizer (DFE) to realize a high-speed dynamic random …
one-tap tri-level decision feedback equalizer (DFE) to realize a high-speed dynamic random …
Rowhammer Attacks in Dynamic Random-Access Memory and Defense Methods
This paper provides a comprehensive overview of the security vulnerability known as
rowhammer in Dynamic Random-Access Memory (DRAM). While DRAM offers many …
rowhammer in Dynamic Random-Access Memory (DRAM). While DRAM offers many …
A 25-Gb/s Single-Ended PAM-4 Receiver With Time-Windowed LSB Decoder for High-Speed Memory Interfaces
This article presents a 25-Gb/s single-ended four-level pulse-amplitude modulation (PAM-4)
receiver with a time-windowed least significant bit (LSB) decoder for high-speed memory …
receiver with a time-windowed least significant bit (LSB) decoder for high-speed memory …
A 1.3–4-GHz quadrature-phase digital DLL using sequential delay control and reconfigurable delay line
A 1.3–4-GHz quadrature-phase digital delay-locked loop (DDLL) with sequential delay
control and a reconfigurable delay line is designed using a 28 nm CMOS process. The time …
control and a reconfigurable delay line is designed using a 28 nm CMOS process. The time …
Dynamic flash memory with dual gate surrounding gate transistor (SGT)
K Sakui, N Harada - 2021 IEEE International Memory Workshop …, 2021 - ieeexplore.ieee.org
This paper proposes an ultra-scaled memory device, called 'Dynamic Flash Memory (DFM)'.
With a dual-gate Surrounding Gate Transistor (SGT), a capacitorless 4F2 cell can be …
With a dual-gate Surrounding Gate Transistor (SGT), a capacitorless 4F2 cell can be …
A 24-Gb/s/pin 8-Gb GDDR6 with a half-rate daisy-chain-based clocking architecture and I/O circuitry for low-noise operation
JH Kang, J Yang, K Kim, JH Chae… - IEEE Journal of Solid …, 2021 - ieeexplore.ieee.org
The demand for high-performance graphics systems used for artificial intelligence, cloud
game, and virtual reality continues to grow; this trend requires graphics systems to achieve …
game, and virtual reality continues to grow; this trend requires graphics systems to achieve …
Data-dependent selection of amplitude and phase equalization in a quarter-rate transmitter for memory interfaces
We combine 2-tap feed-forward amplitude equalization with phase equalization by 4-tap
integrated pulse-width modulation. In a V SS-terminated transmitter, amplitude equalization …
integrated pulse-width modulation. In a V SS-terminated transmitter, amplitude equalization …
A 60-Gb/s 1.2-pJ/bit 1/4-Rate PAM-4 Receiver With a Jitter Compensation CDR
This article presents a four-level pulse amplitude modulation (PAM-4) receiver (Rx) with a
jitter compensation clock and data recovery (JCCDR) for high-speed retimer application …
jitter compensation clock and data recovery (JCCDR) for high-speed retimer application …