[HTML][HTML] Design implementations of ternary logic systems: A critical review

F Zahoor, RA Jaber, UB Isyaku, T Sharma, F Bashir… - Results in …, 2024 - Elsevier
In the electronics industry, binary devices have played a critical role since the development
of solid-state transistors. While binary technology associates devices' inherent ability to be …

Comprehensive survey of ternary full adders: Statistics, corrections, and assessments

S Nemati, M Haghi Kashani… - IET Circuits, Devices & …, 2023 - Wiley Online Library
The history of ternary adders goes back to more than 6 decades ago. Since then, a multitude
of ternary full adders (TFAs) have been presented in the literature. This article conducts a …

High-performance and energy-efficient CNFET-based designs for ternary logic circuits

RA Jaber, A Kassem, AM El-Hajj, LA El-Nimri… - IEEE …, 2019 - ieeexplore.ieee.org
Recently, the demand for portable electronics and embedded systems has increased. These
devices need low-power circuit designs because they depend on batteries as an energy …

Novel ternary adder and multiplier designs without using decoders or encoders

JM Aljaam, RA Jaber, SA Al-Maadeed - IEEE Access, 2021 - ieeexplore.ieee.org
Multiple-Valued Logic systems present significant improvements in terms of energy
consumption over binary logic systems. This paper proposes new ternary combinational …

A novel ultra-low-power CNTFET and 45 nm CMOS based ternary SRAM

AS Vidhyadharan, S Vidhyadharan - Microelectronics Journal, 2021 - Elsevier
This paper presents a CNTFET based ultra-low-power ternary SRAM design which
consumes merely 66 nW of power, achieving 84–98% reduction in power consumption as …

A novel low-energy CNTFET-based ternary half-adder design using unary operators

RA Jaber, B Owaidat, A Kassem… - … on innovation and …, 2020 - ieeexplore.ieee.org
Energy consumption is a critical factor to be reduced when designing embedded systems
and IoT devices. By using Multiple-valued logic (MVL) circuits, interconnections complexity …

1-trit ternary multiplier and adder designs using ternary multiplexers and unary operators

RA Jaber, H Bazzi, A Haidar, B Owaidat… - … on Innovation and …, 2021 - ieeexplore.ieee.org
This work proposes models for a L-trit TMUL (Ternary Multiplier) and THA (Half-Adder) using
TMUXs (Ternary Multiplexers) and unary operators. The target of the proposed designs is to …

Mux based ultra-low-power ternary adders and multiplier implemented with CNFET and 45 nm MOSFETs

AS Vidhyadharan, S Vidhyadharan - International Journal of …, 2022 - Taylor & Francis
This paper presents improved multiplexer-based ultra-low-power ternary Half Adder (HA),
ternary Full Adder (FA), and ternary 1-bit multiplier designs. The proposed circuits consume …

Design of Decoder Using Ternary Inverter

D Manikkule, P Jaronde - 2019 IEEE 5th International …, 2019 - ieeexplore.ieee.org
For the conventional binary logic, ternary logic is the best alternative which is trivalent logic.
Energy efficiency and reduction in chip area as well as complexity plays an important role in …

Multiple-Valued Logic Circuit Design and Data Transmission Intended for Embedded Systems

RA Jaber, L Nimri, AM Haidar - arXiv preprint arXiv:2211.04542, 2022 - arxiv.org
This thesis proposes novel ternary circuits aiming to reduce energy to preserve battery
consumption. The proposed designs include eight ternary logic gates, three ternary …