Multi-layer memory resiliency

N Dutt, P Gupta, A Nicolau, A BanaiyanMofrad… - Proceedings of the 51st …, 2014 - dl.acm.org
With memories continuing to dominate the area, power, cost and performance of a design,
there is a critical need to provision reliable, high-performance memory bandwidth for …

Leveraging on deep memory hierarchies to minimize energy consumption and data access latency on single-chip cloud computers

T Maqsood, N Tziritas, T Loukopoulos… - IEEE Transactions …, 2017 - ieeexplore.ieee.org
Recent advances in chip design and integration technologies have led to the development
of Single-Chip Cloud computers which are a microcosm of cloud datacenters. Those …

REMEDIATE: A scalable fault-tolerant architecture for low-power NUCA cache in tiled CMPs

A BanaiyanMofrad, H Homayoun… - 2013 International …, 2013 - ieeexplore.ieee.org
Technology scaling and process variation severely degrade the reliability of Chip
Multiprocessors (CMPs), especially their large cache blocks. To improve cache reliability, we …

A gals router for asynchronous network-on-chip

PM Yaghini, A Eghbal, N Bagherzadeh - Proceedings of International …, 2014 - dl.acm.org
A scalable asynchronous NoC router with lower power consumption and latency comparing
to a synchronous design is introduced in this article. It employs GALS interfaces …

NoC-based fault-tolerant cache design in chip multiprocessors

A Banaiyanmofrad, G Girao, N Dutt - ACM Transactions on Embedded …, 2014 - dl.acm.org
Advances in technology scaling increasingly make emerging Chip MultiProcessor (CMP)
platforms more susceptible to failures that cause various reliability challenges. In such …

Locality transformations and prediction techniques for optimizing multicore memory performance

AHA Badawy - 2013 - search.proquest.com
Abstract Chip Multiprocessors (CMPs) are here to stay for the foreseeable future. In terms of
programmability of these processors what is different from legacy multiprocessors is that …

Reliable on-chip memory design for cmps

A Banaiyanmofrad - 2012 IEEE 31st Symposium on Reliable …, 2012 - ieeexplore.ieee.org
Aggressive technology scaling in deep sub micron regime makes chips more susceptible to
failures. This causes multiple realibility challenges in the design of modern chips, including …

[PDF][PDF] Energy-Efficient Task and Data Scheduling for Large-Scale Computing Systems

T Maqsood - 2016 - academia.edu
With the recent advancements in integration technologies and aggressive transistor scaling,
dozens or even hundreds of processing cores can be integrated onto a single chip changing …

[图书][B] Resilient On-Chip Memory Design in the Nano Era

A BanaiyanMofrad - 2015 - search.proquest.com
Aggressive technology scaling in the nano-scale regime makes chips more susceptible to
failures. This causes multiple reliability challenges in the design of modern chips, including …

Resource-aware clustering design for NoC-based MPSoCs

GGB Silva - 2014 - lume.ufrgs.br
The multicore paradigm is a solid trend nowadays, also in the field of embedded systems.
The degree of parallelism provided by such architecture has been the foundation of …