Scenario-aware dataflow: Modeling, analysis and implementation of dynamic applications

S Stuijk, M Geilen, B Theelen… - … on Embedded Computer …, 2011 - ieeexplore.ieee.org
Embedded multimedia and wireless applications require a model-based design approach in
order to satisfy stringent quality and cost constraints. The Model-of-Computation (MoC) …

[图书][B] System design, modeling, and simulation: using Ptolemy II

C Ptolemaeus - 2014 - ptolemy.berkeley.edu
In Ptolemy II, models specify computations by composing actors. Many computations,
however, are awkward to specify this way. A common situation is where we wish to evaluate …

A survey on parallelism and determinism

L Gonnord, L Henrio, L Morel, G Radanne - ACM Computing Surveys, 2023 - dl.acm.org
Parallelism is often required for performance. In these situations an excess of non-
determinism is harmful as it means the program can have several different behaviours or …

Taming heterogeneity-the Ptolemy approach

J Eker, JW Janneck, EA Lee, J Liu, X Liu… - Proceedings of the …, 2003 - ieeexplore.ieee.org
Modern embedded computing systems tend to be heterogeneous in the sense of being
composed of subsystems with very different characteristics, which communicate and interact …

Hardware/software codesign: The past, the present, and predicting the future

J Teich - Proceedings of the IEEE, 2012 - ieeexplore.ieee.org
Hardware/software codesign investigates the concurrent design of hardware and software
components of complex electronic systems. It tries to exploit the synergy of hardware and …

[PDF][PDF] Darkroom: compiling high-level image processing code into hardware pipelines.

J Hegarty, JS Brunhaver, Z DeVito, J Ragan-Kelley… - ACM Trans. Graph., 2014 - Citeseer
Specialized image signal processors (ISPs) exploit the structure of image processing
pipelines to minimize memory bandwidth using the architectural pattern of line-buffering …

A clustered manycore processor architecture for embedded and accelerated applications

BD De Dinechin, R Ayrignac… - 2013 IEEE High …, 2013 - ieeexplore.ieee.org
The Kalray MPPA-256 processor integrates 256 user cores and 32 system cores on a chip
with 28nm CMOS technology. Each core implements a 32-bit 5-issue VLIW architecture …

Hierarchical finite state machines with multiple concurrency models

A Girault, B Lee, EA Lee - IEEE Transactions on computer …, 1999 - ieeexplore.ieee.org
This paper studies the semantics of hierarchical finite state machines (FSM's) that are
composed using various concurrency models, particularly dataflow, discrete-events, and …

Parameterized dataflow modeling for DSP systems

B Bhattacharya… - IEEE Transactions on …, 2001 - ieeexplore.ieee.org
Dataflow has proven to be an attractive computation model for programming digital signal
processing (DSP) applications. A restricted version of dataflow, termed synchronous …

A stream compiler for communication-exposed architectures

MI Gordon, W Thies, M Karczmarek, J Lin… - ACM SIGPLAN …, 2002 - dl.acm.org
With the increasing miniaturization of transistors, wire delays are becoming a dominant
factor in microprocessor performance. To address this issue, a number of emerging …