Provided is a delay locked loop (DLL) including a ring oscillator (RO) including a delay line
to delay a reference clock signal and generate a delayed clock signal, wherein the RO …

(Continued) Primary Examiner—Lincoln D Donovan Assistant Examiner—Khareem E Almo
(57) ABSTRACT A multiplying delay-locked loop circuit includes a delay chain including a …

Clock generation from an external reference by generating a reference clock gating signal
using a reference clock gating circuit; enabling a ring-oscillator-injection mode using the …

BACKGROUND For forming a high-frequency local clock from a lower frequency forwarded
clock, a phase-locked loop (PLL) may provide better jitter filtering than a multiplying delay …

(57) ABSTRACT A method and apparatus for synchronizing a delay line to a reference clock
includes a delay line that receives a clock input signal based on a reference clock and …

A clock generation apparatus includes a pulse generator configured to generate a pulse
signal and a selection signal using a reference clock signal, a delay line circuit, a switch and …

A phase delay element coupled to an output of A multiplexor and a first input of the
multiplexor. A reference clock line is coupled to a second input of the multiplexor. A selector …

(57) ABSTRACT A digital phase spacing detector with programmable delay lines is
described. Each programmable delay line receives a clock. The output of the programmable …

BACKGROUND In time to digital converters it is desired to have a good integral nonlinearity
(INL). Gated multipath ring oscillators (GRO) exist which perform a first order shaping. This …

A spur measurement system uses a first device with a spur cancellation circuit that cancel
spurs responsive to a frequency control word identifying a spurious tone of interest. A device …