Systematic exploration of N-Bit Vedic multipliers: A roadmap of technological approaches in pursuit of future trends

H Chugh, S Singh - Nano Communication Networks, 2024 - Elsevier
This review article presents a systematic exploration of N-bit Vedic multipliers, focusing on
the technological approaches utilized for their front-end and back-end stage …

RETRACTED ARTICLE: Performance improvement of elliptic curve cryptography system using low power, high speed 16× 16 Vedic multiplier based on reversible …

S Karthikeyan, M Jagadeeswari - Journal of Ambient Intelligence and …, 2021 - Springer
Multipliers act as processors and take on the notable work of many computing frameworks.
The speed of the processor is profoundly affected by the speed of their multipliers. In order to …

[PDF][PDF] Design and implementation of Vedic multiplier

A Savji, S Oza - International Journal of Recent Technology and …, 2020 - researchgate.net
The ancient vedic mathematics has a set of 16 sutras and 13 subsutras. These sutras give
suitable method for arithmetic calculations. The vedic formulas requires less time than the …

Understanding Mixed Precision GEMM with MPGemmFI: Insights into Fault Resilience

B Fang, X Li, H Dam, C Tan, SKS Hari… - 2024 IEEE …, 2024 - ieeexplore.ieee.org
Emerging deep learning workloads urgently need fast general matrix multiplication (GEMM).
Thus, one of the critical features of machine-learning-specific accelerators such as NVIDIA …

High-Speed Low Area 2D FIR Filter Using Vedic Multiplier

G Nagajyothi, GP Kumar, BS Kumar… - Proceedings of Third …, 2023 - Springer
In this paper, a novel two-dimensional (2D) finite impulse response (FIR) filter is proposed
using Vedic multiplier architecture. Several multipliers, like Vedic, array, Booth, and Wallace …

MPGemmFI: A Fault Injection Technique for Mixed Precision GEMM in ML Applications

B Fang, X Li, H Dam, C Tan, SKS Hari, T Tsai… - arXiv preprint arXiv …, 2023 - arxiv.org
Emerging deep learning workloads urgently need fast general matrix multiplication (GEMM).
To meet such demand, one of the critical features of machine-learning-specific accelerators …

Design and analysis of 32-BiT signed and unsigned multiplier using Booth, Vedic and Wallace Architecture

KM Yong, R Hussin, A Kamarudin… - Journal of Physics …, 2021 - iopscience.iop.org
This paper presents the implementation and performance comparison of the Booth encoding
technique and Wallace Tree reduction scheme on Vedic architecture. The radix-4 Booth …

Comparative Analysis of Vedic Multiplier using Various Adder Architectures

J Yadav, A Kumar, S Shareef, S Bansal… - Journal of Physics …, 2022 - iopscience.iop.org
The performance of a microprocessor depends on the efficient multiplier as it is one of the
most principal component in various digital circuits. This paper reviews optimization …

Implementation of Area and Power efficient components of a MAC unit for DSP Processors

MS Shawl, A Singh, N Gaur, S Bathla… - 2018 Second …, 2018 - ieeexplore.ieee.org
In today's era power, delay and area have become the characteristic features of any VLSI
circuit. Generally, the delay of ordinary multipliers is more and so is the amount of …

Design and implementation of power efficient logic BIST with high fault coverage using verilog

K Akhila, N Karuna, YJM Shirur - … International Conference on …, 2018 - ieeexplore.ieee.org
Due to ever increasing number of transistors on chip and decrease in feature size have
posed challenges in manufacturing and have risen defects due to them. Thus, testing have …