A survey on deep learning hardware accelerators for heterogeneous hpc platforms

C Silvano, D Ielmini, F Ferrandi, L Fiorin… - arXiv preprint arXiv …, 2023 - arxiv.org
Recent trends in deep learning (DL) imposed hardware accelerators as the most viable
solution for several classes of high-performance computing (HPC) applications such as …

Test-driving RISC-V Vector hardware for HPC

JKL Lee, M Jamieson, N Brown, R Jesus - International Conference on …, 2023 - Springer
Abstract Whilst the RISC-V Vector extension (RVV) has been ratified, at the time of writing
both hardware implementations and open source software support are still limited for …

Efficient execution of SpGEMM on long vector architectures

V Le Fèvre, M Casas - … of the 32nd International Symposium on High …, 2023 - dl.acm.org
The Sparse GEneral Matrix-Matrix multiplication (SpGEMM) C= A x B is a fundamental
routine extensively used in domains like machine learning or graph analytics. Despite its …

Spatz: Clustering compact RISC-V-based vector units to maximize computing efficiency

M Perotti, S Riedel, M Cavalcante… - IEEE Transactions on …, 2025 - ieeexplore.ieee.org
The ever-increasing computational and storage requirements of modern applications and
the slowdown of technology scaling pose major challenges to designing and implementing …

Software Development Vehicles to enable extended and early co-design: a RISC-V and HPC case of study

F Mantovani, P Vizcaino, F Banchelli… - … Conference on High …, 2023 - Springer
Prototyping HPC systems with low-to-mid technology readiness level (TRL) systems is
critical for providing feedback to hardware designers, the system software team (eg …

IndexMAC: A Custom RISC-V Vector Instruction to Accelerate Structured-Sparse Matrix Multiplications

V Titopoulos, K Alexandridis, C Peltekis… - … , Automation & Test …, 2024 - ieeexplore.ieee.org
Structured sparsity has been proposed as an efficient way to prune the complexity of modern
Machine Learning (ML) applications and to simplify the handling of sparse data in hardware …

Yun: An open-source, 64-bit RISC-V-Based vector processor with multi-precision integer and floating-point support in 65-nm CMOS

M Perotti, M Cavalcante, A Ottaviano… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
The nature and heterogeneity of modern workloads force hardware designers to choose
between general-purpose processors, which come with superior flexibility, and highly …

QUETZAL: Vector Acceleration Framework for Modern Genome Sequence Analysis Algorithms

J Pavon, IV Valdivieso, C Rojas… - 2024 ACM/IEEE 51st …, 2024 - ieeexplore.ieee.org
Genome sequence analysis is fundamental to medical breakthroughs such as developing
vaccines, enabling genome editing, and facilitating personalized medicine. The …

Short reasons for long vectors in HPC CPUs: a study based on RISC-V

P Vizcaino, G Ieronymakis, N Dimou… - Proceedings of the SC' …, 2023 - dl.acm.org
For years, SIMD/vector units have enhanced the capabilities of modern CPUs in High-
Performance Computing (HPC) and mobile technology. Typical commercially-available …

SySMOL: A Hardware-software Co-design Framework for Ultra-Low and Fine-Grained Mixed-Precision Neural Networks

C Zhou, V Richard, P Savarese, Z Hassman… - arXiv preprint arXiv …, 2023 - arxiv.org
Recent advancements in quantization and mixed-precision techniques offer significant
promise for improving the run-time and energy efficiency of neural networks. In this work, we …