Design of Low Power High-Speed SAR ADC-A Review
PS Devitha, A George - 2019 3rd International Conference on …, 2019 - ieeexplore.ieee.org
Data converters play an important role in this ever-increasing digital world, which is mainly
dependent on Complementary Metal Oxide Semiconductor (CMOS) technology. Analog to …
dependent on Complementary Metal Oxide Semiconductor (CMOS) technology. Analog to …
A 1-V 690 μW 8-bit 200 MS/s flash-SAR ADC with pipelined operation of flash and SAR ADCs in 0.13 μm CMOS
M Eslami, M Taherzadeh-Sani… - 2015 IEEE International …, 2015 - ieeexplore.ieee.org
The successive-approximation-register (SAR) analog-to-digital converter (ADC) has recently
attracted a lot of interest due to its power efficiency as well as its simple structure. The main …
attracted a lot of interest due to its power efficiency as well as its simple structure. The main …
Power efficient SAR ADC designed in 90 nm CMOS technology
A 8-bit Successive Approximation Register (SAR) Analog to Digital Converter (ADC) is
designed using non redundant SAR structure and sequencer/code Register structure for low …
designed using non redundant SAR structure and sequencer/code Register structure for low …
8-bit 250-MS/s ADC Based on SAR Architecture with Novel Comparator at 70 nm Technology Node
The data converters are prerequisite for digital processing of analog signals. SAR ADC is
preferred for their good balance between speed, area and power considerations. In this …
preferred for their good balance between speed, area and power considerations. In this …
Pipelining method for low-power and high-speed SAR ADC design
Z Fazel, S Saeedi, M Atarodi - Analog Integrated Circuits and Signal …, 2016 - Springer
A low power analog to digital converter (ADC), based on a pipelining method employed in
successive approximation register (SAR) architecture is presented. This structure is a two …
successive approximation register (SAR) architecture is presented. This structure is a two …
A 10-bit 300-MS/s asynchronous SAR ADC with strategy of optimizing settling time for capacitive DAC in 65 nm CMOS
Abstract A 10-bit 300-MS/s asynchronous SAR ADC in 65 nm CMOS is presented in this
paper. To achieve low power, binary-weighed capacitive DAC is employed without any …
paper. To achieve low power, binary-weighed capacitive DAC is employed without any …
Towards the introduction of the asymmetric cryptography in GSM, GPRS, and UMTS networks
CF Grecas, SI Maniatis… - Proceedings. Sixth IEEE …, 2001 - ieeexplore.ieee.org
The logic ruling the user and network authentication as well as the data ciphering in the
GSM architecture has been inherited by the General Packet Radio Services (GPRS) and the …
GSM architecture has been inherited by the General Packet Radio Services (GPRS) and the …
Methods to Improve Linearity of Signal's Analog-to-Digital Conversion with Self-Calibration
V Melikyan - Machine Learning-based Design and Optimization of …, 2023 - Springer
This chapter is devoted to the development of embedded methods for ADCs and DACs,
which will allow to reduce the impact of errors after manufacturing process through self …
which will allow to reduce the impact of errors after manufacturing process through self …
8-Bit high speed, power efficient SAR ADC designed in 90 nm CMOS technology
In this work a high speed, power efficient successive approximation register (SAR) analog to
digital converter (ADC) is designed using 90nm CMOS technology. Double tail dynamic …
digital converter (ADC) is designed using 90nm CMOS technology. Double tail dynamic …
[图书][B] Machine Learning-based Design and Optimization of High-Speed Circuits
V Melikyan - 2024 - Springer
The book systematically expounds the main results obtained by the author in the field of
design and optimization of high-speed integrated circuits (ICs) and their standard blocks …
design and optimization of high-speed integrated circuits (ICs) and their standard blocks …