[HTML][HTML] Time-to-digital conversion techniques: A survey of recent developments

J Szyduczyński, D Kościelnik, M Miśkowicz - Measurement, 2023 - Elsevier
Time-to-digital converters (TDCs) are key components of time-mode circuits and enablers for
digital processing of analog signals encoded in time. Since design of time-mode circuits …

CMOS time-to-digital converters for biomedical imaging applications

R Scott, W Jiang, MJ Deen - IEEE Reviews in Biomedical …, 2021 - ieeexplore.ieee.org
Time-to-digital converters (TDCs) are high-performance mixed-signal circuits capable of
timestamping events with sub-gate delay resolution. As a result of their high-performance, in …

A 3.7 mW low-noise wide-bandwidth 4.5 GHz digital fractional-N PLL using time amplifier-based TDC

A Elkholy, T Anand, WS Choi, A Elshazly… - IEEE Journal of Solid …, 2015 - ieeexplore.ieee.org
A digital fractional-N PLL that employs a high resolution TDC and a truly ΔΣ fractional divider
to achieve low in-band noise with a wide bandwidth is presented. The fractional divider …

An adaptive pre-distortion technique to mitigate the DTC nonlinearity in digital PLLs

S Levantino, G Marzin, C Samori - IEEE Journal of Solid-State …, 2014 - ieeexplore.ieee.org
Digital fractional-N phase-locked loops (PLLs) are an attractive alternative to analog PLLs in
the design of frequency synthesizers for wireless applications. However, the main obstacle …

A 12.08-TOPS/W all-digital time-domain CNN engine using bi-directional memory delay lines for energy efficient edge computing

A Sayal, SST Nibhanupudi, S Fathima… - IEEE Journal of Solid …, 2019 - ieeexplore.ieee.org
In this article, we demonstrate an energy efficient convolutional neural network (CNN)
engine by performing multiply-and-accumulate (MAC) operations in the time domain. The …

A 2.3-mW, 1-GHz, 8-bit fully time-based two-step ADC using a high-linearity dynamic VTC

K Ohhata - IEEE Journal of Solid-State Circuits, 2019 - ieeexplore.ieee.org
A novel fully time-based two-step analog-to-digital converter (ADC) is proposed. Two time-
based ADCs (TB ADCs) are used for coarse ADC (CADC) and fine ADC (FADC), resulting in …

Low power and small area, 6.9 ps RMS time-to-digital converter for 3-D digital SiPM

N Roy, F Nolet, F Dubois, MO Mercier… - … on Radiation and …, 2017 - ieeexplore.ieee.org
Time-of-flight measurements are becoming essential to the advancement of several fields,
such as preclinical positron emission tomography and high energy physics. Recent …

A 0.22 ps rms integrated noise 15 MHz bandwidth fourth-order ΔΣ time-to-digital converter using time-domain error-feedback filter

W Yu, KS Kim, SH Cho - IEEE Journal of solid-state circuits, 2015 - ieeexplore.ieee.org
In this paper, a fourth-order ΔΣ time-to-digital converter (TDC) is proposed to achieve high
resolution and wide signal bandwidth. The proposed TDC is based on a 1-3 multi-stage …

COMPAC: Compressed time-domain, pooling-aware convolution CNN engine with reduced data movement for energy-efficient AI computing

A Sayal, S Fathima, SST Nibhanupudi… - IEEE Journal of Solid …, 2020 - ieeexplore.ieee.org
In this work, we demonstrate a compressed time-domain, pooling-aware convolution
(COMPAC) convolutional neural network (CNN) engine for energy-efficient edge AI …

A 10-GS/s 8-bit 2850-μm2 Two-Step Time-Domain ADC With Speed and Efficiency Enhanced by the Delay-Tracking Pipelined-SAR TDC

J Liu, M Hassanpourghadi… - IEEE Journal of Solid …, 2022 - ieeexplore.ieee.org
This article presents an 8-bit time-domain analog-to-digital converter (ADC) achieving ten-
GS/s conversion speed with only two time-interleaved (TI) channels. A successive …