Design of Dynamic comparator using CMOS and FINFET technologies
KLVR Kumari, LP Sree, P Raji - 2023 14th International …, 2023 - ieeexplore.ieee.org
A two-stage and three-stage dynamic comparator architecture is proposed using FINFET
technology for high speed, low power dissipation and comparison is done between three …
technology for high speed, low power dissipation and comparison is done between three …
Implementation of CMOS Logic Gates Using ASiNR-based TFET
Silicene has drawn wide attention as a promising candidate for potential application in the
semiconductor industry because of its two-dimensional structure and the possibility of a …
semiconductor industry because of its two-dimensional structure and the possibility of a …
[PDF][PDF] Low Kickback Noise and High-Speed Multistage Comparator for High-Speed SAR ADC's
AK Dharmireddy, D Sowjanya, D Aravind, G Sowmya… - 2024 - ijmit.org
In this paper, proposes the design of a high-speed, low-kickback, three-stage comparator
built on CMOS technology. This 1.2 V supply-operated comparator circuit develops for use in …
built on CMOS technology. This 1.2 V supply-operated comparator circuit develops for use in …