Dynamic voltage (IR) drop analysis and design closure: Issues and challenges

SK Nithin, G Shanmugam… - 2010 11th International …, 2010 - ieeexplore.ieee.org
Dynamic voltage (IR) drop, unlike the static voltage drop depends on the switching activity of
the design, and hence it is vector dependent. In this paper we have highlighted the pitfalls in …

Power gating: Circuits, design methodologies, and best practice for standard-cell VLSI designs

Y Shin, J Seomun, KM Choi, T Sakurai - ACM Transactions on Design …, 2010 - dl.acm.org
Power Gating has become one of the most widely used circuit design techniques for
reducing leakage current. Its concept is very simple, but its application to standard-cell VLSI …

Design techniques for NBTI-tolerant power-gating architectures

A Calimera, E Macii, M Poncino - IEEE Transactions on Circuits …, 2012 - ieeexplore.ieee.org
While negative bias temperature instability (NBTI) effects on logic gates are of major concern
for the reliability of digital circuits, they become even more critical when considering the …

Ground-bouncing-noise-aware combinational MTCMOS circuits

H Jiao, V Kursun - IEEE Transactions on Circuits and Systems I …, 2010 - ieeexplore.ieee.org
Ground bouncing noise produced during the SLEEP to ACTIVE mode transitions is an
important challenge in standard multithreshold CMOS (MTCMOS) circuits. The effectiveness …

Linear-phase delay filters for ultra-low-power signal processing in neural recording implants

B Gosselin, M Sawan… - IEEE transactions on …, 2010 - ieeexplore.ieee.org
We present the design and implementation of linear-phase delay filters for ultra-low-power
signal processing in neural recording implants. We use these filters as low-distortion delay …

Reliable power gating with NBTI aging benefits

D Rossi, V Tenentes, S Yang… - … Transactions on Very …, 2016 - ieeexplore.ieee.org
In this paper, we show that negative bias temperature instability (NBTI) aging of sleep
transistors (STs), together with its detrimental effect for circuit performance and lifetime (LT) …

Design of a flexible reactivation cell for safe power-mode transition in power-gated circuits

A Calimera, L Benini, A Macii, E Macii… - IEEE Transactions on …, 2008 - ieeexplore.ieee.org
Power-gating is one of the most promising and widely adopted solutions for controlling sub-
threshold leakage power in nanometer circuits. Although single-cycle power-mode transition …

Multibit retention registers for power gated designs: Concept, design, and deployment

YG Chen, H Geng, KY Lai, Y Shi… - IEEE Transactions on …, 2014 - ieeexplore.ieee.org
Retention registers have been widely used in power gated designs to store data during
sleep mode. However, their excessive area and leakage power render it imperative to …

NBTI and leakage aware sleep transistor design for reliable and energy efficient power gating

D Rossi, V Tenentes, S Khursheed… - 2015 20th IEEE …, 2015 - ieeexplore.ieee.org
In this paper we show that power gating techniques become more effective during their
lifetime, since the aging of sleep transistors (STs) due to negative bias temperature …

Power-gating-aware high-level synthesis

E Choi, C Shin, T Kim, Y Shin - … of the 2008 international symposium on …, 2008 - dl.acm.org
A problem inherent in designing power-gated circuits is the overhead of the state-retention
storage required to preserve the circuit state in standby mode. Reducing the amount of …