2005-08-05 Assigned to PACT XPP TECHNOLOGIES AG reassignment PACT XPP
TECHNOLOGIES AG ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR …

(57) ABSTRACT A cascadable arithmetic and logic unit (ALU) which is con figurable in
function and interconnection. No decoding of commands is needed during execution of the …

Abstract The domain of Field-Programmable Gate Arrays (FPGAs) has undergone a
dramatic revolution in the past decade. What started as a cheap alternative to custom design …

(57) ABSTRACT A data processing device comprising a multidimensional array of coarse
grained logic elements processing data and operating at a? rst clock rate and …

In a data-processing method, first result data may be obtained using a plurality of
configurable coarse-granular elements, the first result data may be written into a memory …

3,242.998 A 3, 1966 Gubbins 5,327,125 A 7, 1994 Iwase et al. 3,681,578 A 8, 1972 Stevens
5,336,950 A 8/1994 Popli et al. 3,757,608 A 9, 1973 Willner 5,343,406 A 8, 1994 Freeman et …

3,242,998 3,681,578 3,757,608 3,855,577 4,233,667 4.414, 547 4,498,134 4,498,172
4,566,102 4,571,736 4,590,583 4,591,979 4,663,706 4,667,190 4,682,284 4,686,386 …

3,753,008 3,754,211 3,855,577 3,956,589 4,151,611 4,233,667 4.414, 547 4,498,134
4,498,172 4,566,102 4,571,736 4,590,583 4,591,979 4,594,682 4,623,997 4,646,300 …

In a system including a multidimensional field of reconfigurable elements, and a method for
operating said field of reconfigurable elements, one or more groups of said elements …

A reconfigurable processor (VPU) is designed for a technical environment having a standard
processor (CPU) which has, for example, a DSP, RISC, CISC processor or a (micro) …