Sequential particle swarm optimization for visual tracking

X Zhang, W Hu, S Maybank, X Li… - 2008 IEEE conference on …, 2008 - ieeexplore.ieee.org
Visual tracking usually involves an optimization process for estimating the motion of an
object from measured images in a video sequence. In this paper, a new evolutionary …

Balanced self-checking asynchronous logic for smart card applications

S Moore, R Anderson, R Mullins, G Taylor… - Microprocessors and …, 2003 - Elsevier
Delay-insensitive or unordered codes may be used to construct both robust asynchronous
circuits and self-checking systems. The redundant nature of the coding scheme also …

Asynchronous design—Part 2: Systems and methodologies

SM Nowick, M Singh - IEEE Design & Test, 2015 - ieeexplore.ieee.org
This two-part article aims to provide both a short historical and technical overview of
asynchronous design, as well as a snapshot of the state of the art. Part 1 covered …

Efficient failure detection in pipelined asynchronous circuits

S Peng, R Manohar - … on Defect and Fault Tolerance in VLSI …, 2005 - ieeexplore.ieee.org
This paper presents an efficient concurrent failure detection method for pipelined
asynchronous circuits. We first validate permanent and transient fault modeling in clockless …

Error-correcting unordered codes and hardware support for robust asynchronous global communication

MY Agyekum, SM Nowick - IEEE Transactions on Computer …, 2011 - ieeexplore.ieee.org
This paper introduces a new family of error-correction unordered (ECU) codes for global
communication, called Zero-Sum. They combine the timing-robustness of delay-insensitive …

Self-timed section-carry based carry lookahead adders and the concept of alias logic

P Balasubramanian, DA Edwards… - Journal of Circuits …, 2013 - World Scientific
This paper makes two important contributions to the domain of self-timed computer
arithmetic. Firstly, a gate-level synthesis of self-timed carry lookahead (CLA) adders based …

Concurrent error detection methods for asynchronous burst-mode machines

S Almukhaizim, Y Makris - IEEE Transactions on Computers, 2007 - ieeexplore.ieee.org
Asynchronous controllers exhibit various characteristics that limit the effectiveness and
applicability of the concurrent error detection (CED) methods developed for their …

Membership test logic for delay-insensitive codes

SJ Piestrak - … on Advanced Research in Asynchronous Circuits …, 1998 - ieeexplore.ieee.org
Delay-insensitive (unordered) codes have been used to encode data in various
asynchronous systems such as asynchronous circuits and buses. In this paper, a new …

[图书][B] Self-timed logic and the design of self-timed adders

B Padmanabhan, D Edwards - 2010 - apt.cs.manchester.ac.uk
A majority of the present-day digital systems are clock based or synchronous, which assume
that signals are binary and time is discrete. In general, synchronous systems comprise a …

Novel hazard-free majority voter for N-modular redundancy-based fault tolerance in asynchronous circuits

S Almukhaizim, O Sinanoglu - IET Computers & Digital Techniques, 2011 - IET
N-modular redundancy (NMR) is the simplest and most effective fault-tolerant design
method for integrated circuits, where N copies of a circuit are employed and a majority voter …