This paper investigates the potential of using strong BCH codes to improve multilevel data-
storage NAND Flash memory capacity. Current multilevel Flash memories store 2 bits in …

The design of on-chip error correction systems for multilevel code-storage NOR flash and
data-storage NAND flash memories is concerned. The concept of trellis coded modulation …

Method and apparatus for managing data in a memory, such as a flash memory array. In
accordance with various embodiments, a first data access operation is conducted on a …

This paper presents a synthetic overview of multilevel (ML) flash memory program methods.
The problem of increasing program time with the number of bits stored in each cell is …

Garbage collection (GC) is time consuming and frequently executed all over the lifetime of
solid-state drives (SSDs), which has a significant impact on system performance …

A construction using the E8 lattice and Reed-Solomon codes for error-correction in flash
memory is given. Since E8 lattice decoding errors are bursty, a Reed-Solomon code over GF …

Redundant arrays of independent disk (RAID) is an efficient approach to relieve reliability
sacrifice caused by aggressive scale-out of solid state drives (SSDs). Unfortunately, RAID is …

This paper presents an implementation for improving muti-level cell NOR flash memory
program throughput based on the channel hot electron (CHE) temperature characteristic …

This paper gives an overview of the author's recent results on using lattices for error-
correction and rewriting in flash memories. A construction using the E8 lattice and Reed …

Well-defined experimental and simulating single peak to valley current density ratio
(PVCDR) resonant tunneling electronic circuit (RTEC) element is proposed in this research …