Machine learning enabled solutions for design and optimization challenges in networks-on-chip based multi/many-core architectures

MF Reza - ACM Journal on Emerging Technologies in Computing …, 2023 - dl.acm.org
Due to the advancement of transistor technology, a single chip processor can now have
hundreds of cores. Network-on-Chip (NoC) has been the superior interconnect fabric for …

A study of a wire–wireless hybrid NoC architecture with an energy-proportional multicast scheme for energy efficiency

P Dai, J Chen, Y Zhao, YH Lai - Computers & Electrical Engineering, 2015 - Elsevier
The efficiency of interconnect network-on-chip (NoC) design significantly affects the thermal
and energy-consumption problems. The wireless interconnect NoC (WiNoC) design …

OWBM: OSNR-Aware Wavelength Allocation and Branching Methods for Multicast Routing in Custom Topology-Based Optical Network-on-Chips

YW Kim, TH Han - IEEE Access, 2024 - ieeexplore.ieee.org
In light of the rapid advancements in big data and artificial intelligence applications,
heterogeneous computing (HGC) platforms that integrate diverse computing units have …

Modeling and Performance Analysis of a Fault‐Tolerant 3D Photonic Network‐on‐Chip Based on Hybrid Photonics–Plasmonics

L Zhixun, X Chuanpei, B Lvqing… - Computational …, 2022 - Wiley Online Library
The performance of electro‐optic modulators and optical routers and their routing algorithms
are the key factors affecting the performance of networks on optical chips. This paper …

Hybrid circuit-packet switch

T Morris, CF Clark, RG Beausoleil - US Patent 10,212,497, 2019 - Google Patents
ABSTRACT A hybrid circuit-packet switch device includes a packet switch and a circuit
switch. The circuit switch selectively passes, under control of a control logic, incoming data …

A scalable software defined network orchestrator for photonic network on chips

DA Hamdi, S Ghoniemy, Y Dakroury, MA Sobh - IEEE Access, 2021 - ieeexplore.ieee.org
Photonic networks and software-defined networks are two promising technologies to
improve network-on-chips performance, scalability, and resource utilization. Several …

Research on topology and policy for low power consumption of network-on-chip with multicore processors

J Fang, J Lu, C She - 2015 International Conference on …, 2015 - ieeexplore.ieee.org
On-chip multi-processor technology has developed rapidly with progress in manufacturing
processes, resulting in a continuous increase in the number of processor cores on a chip …

A blocking optimization method by convergence of cores for application-based optical circuit switched network-on-chip

W Xu, N Wu, B Liu - Microprocessors and Microsystems, 2017 - Elsevier
With the development of technology of integrated circuit (IC), there will be several hundred
million or even several billion transistors in one chip. Optical network on chip (ONoC) has …

Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems

A Roca, C Hernandez, M Lodde, J Flich - Computers & Electrical …, 2015 - Elsevier
Manycore CMP systems are expected to grow to tens or even hundreds of cores. In this
paper we show that the effective co-design of both, the network-on-chip and the coherence …

Butha: Boost up clock terminal with heuristic approach for NoC

E Sakthivel, V Malathi, M Arunraja - Journal of Circuits, Systems and …, 2018 - World Scientific
In recent days, there has been a growing interest in network-on-chip (NoC), as it offers a
promising architecture for future systems on-chip (SoC). The performance degradation is the …