Review of the nanoscale FinFET device for the applications in nano-regime
Background: The insatiable need for low-power and high-performance integrated circuit (IC)
results in the development of alternative options for metal oxide semiconductor field effect …
results in the development of alternative options for metal oxide semiconductor field effect …
Taming molecular field-coupling for nanocomputing design
Molecular Field-Coupling Nanocomputing (FCN) is one of the most promising technologies
for overcoming Complementary Metal Oxide Semiconductor (CMOS) scaling issues. It …
for overcoming Complementary Metal Oxide Semiconductor (CMOS) scaling issues. It …
Energy efficient and variability immune adder circuits using short gate FinFET INDEP technique at 10nm technology node
Due to the continuous scaling of MOSFET (Metal Oxide Semiconductor Field-Effect
Transistor) devices over the past few decades, power consumption has increased …
Transistor) devices over the past few decades, power consumption has increased …
The impact of channel fin width on electrical characteristics of Si-FinFET
Y Hashim - International Journal of Electrical and Computer …, 2022 - eprints.tiu.edu.iq
This paper studies the impact of fin width of channel on temperature and electrical
characteristics of fin field-effect transistor (FinFET). The simulation tool multi-gate field effect …
characteristics of fin field-effect transistor (FinFET). The simulation tool multi-gate field effect …
[PDF][PDF] Ultra-low-voltage and high-speed 1-bit full adder cell using finfet transistors for mobile applications
AB Rahin, VB Rahin - International Journal of Mechatronics …, 2018 - academia.edu
Full Adder is the building block of computing circuits. Designing a Full Adder with the smaller
area, low power consumption, and high-speed have always been demanded. Since the …
area, low power consumption, and high-speed have always been demanded. Since the …
Intelligent signal gating-aware energy-efficient 8-bit FinFET arithmetic and logic unit
D Ajitha, M Chandra Sekhar Reddy - Circuits, Systems, and Signal …, 2022 - Springer
A FinFET-based 8-bit low-power arithmetic and logic unit (ALU) with full-swing 9-transistor
GDI-hybrid full adder has been presented in this research paper. An intelligent signal gating …
GDI-hybrid full adder has been presented in this research paper. An intelligent signal gating …
Design and Analysis of Low Power FinFET-Based Hybrid Full Adders at 16 nm Technology Node
In the current trend technology, where portable electronic devices are used in our day-to-day
life, the development of the electronic circuits which consumes low power with optimum …
life, the development of the electronic circuits which consumes low power with optimum …
Comparative Analysis of EEPL and PPL Techniques in 18nm FinFET Technology
G Rana, K Sharma, A Sharma, L Gupta… - 2023 IEEE Devices …, 2023 - ieeexplore.ieee.org
Pass Transistor Logic characterizes several logic families by eliminating redundant MOS
transistors from the CMOS digital architecture. This logic can be effectively employed to …
transistors from the CMOS digital architecture. This logic can be effectively employed to …
A proposed reliable and power efficient 14T full adder circuit design
S Subramaniam, TWX Wilson… - TENCON 2017-2017 …, 2017 - ieeexplore.ieee.org
This paper presents design of a new stable 14T full power efficient adder circuit. The
proposed circuit is designed based on Pass Transistor Logic (PTL) network using NMOS …
proposed circuit is designed based on Pass Transistor Logic (PTL) network using NMOS …
Configuring a Hybrid Full Adder Using Strained-Si Channel DG JLT with Work Function Modulation
The impact of the work function modulation (WFM) in sub-20nm strained silicon channel
double gate (SSCDG) junctionless transistor (JLT) is explored in this article for low power …
double gate (SSCDG) junctionless transistor (JLT) is explored in this article for low power …