Heteroflow: An accelerator programming model with decoupled data placement for software-defined fpgas

S Xiang, YH Lai, Y Zhou, H Chen, N Zhang… - Proceedings of the …, 2022 - dl.acm.org
To achieve high performance with FPGA-equipped heterogeneous compute systems, it is
crucial to co-optimize data placement and compute scheduling to maximize data reuse and …

Fluid: An asynchronous high-level synthesis tool for complex program structures

R Li, L Berkley, Y Yang… - 2021 27th IEEE …, 2021 - ieeexplore.ieee.org
Current high-level synthesis (HLS) tools that generate synchronous logic construct a state
machine that schedules program operations in each clock cycle. Rather than this centralized …

An automated design flow for adaptive neural network hardware accelerators

F Ratto, ÁP Máinez, C Sau, P Meloni, G Deriu… - Journal of Signal …, 2023 - Springer
Image and video processing are one of the main driving application fields for the latest
technology advancement of computing platforms, especially considering the adoption of …

The Multi-Dataflow Composer tool: An open-source tool suite for optimized coarse-grain reconfigurable hardware accelerators and platform design

C Sau, T Fanni, C Rubattu, L Raffo… - Microprocessors and …, 2021 - Elsevier
Modern embedded and cyber-physical systems require every day more performance, power
efficiency and flexibility, to execute several profiles and functionalities targeting the ever …

Run-time performance monitoring of heterogenous hw/sw platforms using papi

T Fanni, D Madronal, C Rubattu, C Sau… - FSP Workshop 2019; …, 2019 - ieeexplore.ieee.org
In the era of Cyber Physical Systems, designers need to offer support for run-time adaptivity
considering different constraints, including the internal status of the system. This work …

FPGA-based Implementation for Industrial Motion Control System

C Rubattu, A Ledda, F Ratto, C Jugade… - 2024 IEEE …, 2024 - ieeexplore.ieee.org
In these years of severe chip shortage, it is even more important to improve the efficiency of
chip manufacturing. As is well known, manufacturing phases rely on increasingly intelligent …

Mutual impact between clock gating and high level synthesis in reconfigurable hardware accelerators

F Ratto, T Fanni, L Raffo, C Sau - Electronics, 2021 - mdpi.com
With the diffusion of cyber-physical systems and internet of things, adaptivity and low power
consumption became of primary importance in digital systems design. Reconfigurable …

Feasibility Study and Porting of the Damped Least Square Algorithm on FPGA

C Sau, T Fanni, C Rubattu, L Fanni, L Raffo… - Ieee …, 2020 - ieeexplore.ieee.org
Modern embedded computing platforms used within Cyber-Physical Systems (CPS) are
nowadays leveraging more and more often on heterogeneous computing substrates, such …

[PDF][PDF] High-level Synthesis Parallelization and Optimization of Vectorized Self-organizing Maps

OX Rivera-Morales - 2022 - lutzhamel.github.io
The nature of the Self-Organized Maps (SOM) requires a constant improvement of
performance to address the increasing complexity of datasets. These demands have led to …

ACQuA: A Parallel Accelerator Architecture for Pure Functional Programs

R Coelho, F Tanus, Á Moreira… - 2020 IEEE Computer …, 2020 - ieeexplore.ieee.org
Typical reconfigurable accelerators are either limited to instruction-level parallelism or
require developers to manage parallelism in the source code manually. Pure functional …