Current computing platforms encourage the integration of thousands of processing cores,
and their interconnections, into a single chip. Mobile smartphones, IoT, embedded devices …

The multilayer structure of 3-D network-on-chips (3-D NoC) leads to the unequal thermal
conductance between different layers and, as a result, an unbalanced thermal distribution in …

Abstract 3D Network on Chips (NoCs) have been widely used in recent years to improve the
performance comparing 2D NoCs. They employ TSVs to connect different layers in the stack …

Die-stacking technology is expanding the space diversity of on-chip communications by
leveraging through-silicon-via (TSV) integration and wafer bonding. The 3D network-on-chip …

Due to high manufacturing cost of Through Silicon Via (TSV) in 3D Network-on-Chips
(NoCs), not every router is vertically connected. In most 3D NoCs only a subset of TSVs are …

The die-stacking structure of 3D network-on-chips (3D NoC) leads to high power density and
unequal thermal conductance between different layers, which results in low reliability and …

Abstract Although many Dynamic Thermal Management (DTM) techniques are employed to
overcome thermal problems in 3D NoCs, none of them consider temperature information of …

3D Network-on-chip architecture outperforms 2D ones in terms of area and latency. Layers
in 3D NoC are connected by Through-Silicon Via (TSV), which imposes high implementation …

" By technology scaling and integrating many cores on a chip, two-dimensional (2D) NOCs
face significant challenges. Three-dimensional (3D) NoCs have been introduced to improve …

Due to the stacking dies and unequal cooling effiency of different layers, 3D NoC-based
systems suffer sever thermal issues. Adaptive routing can alleviate the thermal issues, but …