Analysis of 6 T SRAM cell in sub-45 nm CMOS and FinFET technologies

RB Almeida, CM Marques, PF Butzen, FRG Silva… - Microelectronics …, 2018 - Elsevier
The semiconductor industry is exploring technology scaling to pursuit the Moore's Law. The
actual processors operation frequency grows the need for fast memories. Nowadays, SRAM …

[HTML][HTML] An efficient common source sense amplifier for single ended SRAM

J Leavline, A Sugantha - Memories-Materials, Devices, Circuits and …, 2023 - Elsevier
Sense amplifiers (SA) play a vital role in supporting the read performance of static random-
access memory (SRAM). Single ended SRAM has attracted importance due to low leakage …

Low power single bitline 6T SRAM cell with high read stability

B Majumdar, S Basu - … on recent trends in information systems, 2011 - ieeexplore.ieee.org
This paper presents a novel CMOS 6-transistor SRAM cell for different purposes including
low power embedded SRAM applications and stand-alone SRAM applications. The data is …

Effect of Work Function Tuning over the Device Characteristics of GAA SNSTFT

J Sampson, SP, V SP - Silicon, 2023 - Springer
This article talks about optimization of a p-channel Gate All Around Stacked Nano Sheet
Thin Film Transistor (GAA SNSTFT) using Titatium Nitride (TiN) as the gate material. The …

A low power 4T2C nvSRAM with dynamic current compensation operation scheme

C Liu, J Yang, P Jiang, Q Wang… - … Transactions on Very …, 2020 - ieeexplore.ieee.org
This study proposed a novel nonvolatile static random access memory (nvSRAM) cell with
two ferroelectric capacitors (FeCAPs) embedded inside a 4T SRAM cell, ie, 4T2C, for …

Analyzing the low power techniques in sram cells at 45nm node technology

S Dhariwal, AK Thomas, R Korah… - 2024 IEEE 4th …, 2024 - ieeexplore.ieee.org
This paper presents Gated Vdd and MTCMOS techniques to achieve low power from the
simulated static random-access memory (SRAM) cells. These techniques are implemented …

Evaluation of hybrid MRAM/CMOS cells for “normally-off and instant-on” computing

B Jovanović, RM Brum, L Torres - Analog Integrated Circuits and Signal …, 2014 - Springer
To meet the ever-growing demand for higher computing throughput, the clock frequency of
the processor was continually increased. After decades of success, this trend stopped at …

MTJ-based hybrid storage cells for “normally-off and instant-on” computing

B Jovanovic, RM Brum, L Torres - Facta Universitatis, Series …, 2015 - casopisi.junis.ni.ac.rs
Besides increasing a computing throughput, multi-core processor architectures bring
increased capacity of SRAM-based cache memory. As a result, cache memory now …

Design and benchmark of iso-stable high density 4t sram cells for 64mb arrays in 65nm lstp

R Kumar, S Baunthiyal, R Tewari… - 2020 IEEE 17th India …, 2020 - ieeexplore.ieee.org
Embedded SRAMs enable high performance operation of processor and become an
essential block in modern SoCs. Memory instances occupy almost 70% of area of the …

Low Leakage and High Speed Sub-threshold 128-bit Fin-FET SRAM for Ultra-Low-Power Applications

TV Reddy, KM Rao, RA Reddy… - 2023 3rd International …, 2023 - ieeexplore.ieee.org
The demand for Low power handheld devices are rapidly increasing in the recent past and
memory is the heart of the processor. SRAM architecture of Fin-FETs is the most emerging …