(57) ABSTRACT A semiconductor structure includes a substrate having a first region and a
second region, a first source/drain disposed on the substrate in the first region, an interlevel …

(57) ABSTRACT A system and method for efficiently creating layout for a standard cell are
described. A standard cell to be used for an integrated circuit uses a full trench silicide strap …

(57) ABSTRACT A technique relates to a semiconductor device. A first trench silicide (TS) is
coupled to a first source or drain (S/D). A second TS is coupled to a second S/D, and a gate …

Complementary metal oxide semiconductor (MOS)(CMOS) standard cell circuits employing
metal lines in a first metal layer used for routing, and related methods are disclosed. In one …

An embodiment of a semiconductor switch structure includes source contacts, drain
contacts, gates and fins. The contacts and gates are elongated in a first direction and are …

A method for forming a semiconductor structure is provided. The method includes depositing
a dielectric material in a first opening above a first source/drain region in a first region of the …

At least one method, apparatus and system disclosed herein for forming a finFET device
having a pass-through structure. A first gate structure and a second gate structure are …

(57) ABSTRACT A system and method for creating chip layout are described. In various
embodiments, a standard cell uses unidirectional tracks for power connections and signal …

Structures for a field-effect transistor and methods of form ing a structure for field-effect
transistor. A gate structure includes a work function metal layer, a first conductor layer, and a …

(57) ABSTRACT A first TS is coupled to first S/D over first fin, second TS coupled to second
S/D over first fin, third TS coupled to third S/D over second fin, fourth TS coupled to fourth …