[PDF][PDF] Braun's multiplier implementation using fpga with bypassing techniques

R Anitha, V Bagyaveereswaran - International Journal of VLSI …, 2011 - research.vit.ac.in
The developing an Application Specific Integrated Circuits (ASICs) will cost very high, the
circuits should be proved and then it would be optimized before implementation …

[PDF][PDF] Low power multiplier with alternative bypassing implementation

GL Jiang, TC Wu, YJ Chang - Proceedings of the International …, 2012 - world-comp.org
As portable devices have become increasingly popular, power reduction has become an
important issue in device design. Because traditional row-bypassing multipliers and column …

FPGA implementation of Braun's multiplier using spartan-3e, Virtex–4, Virtex-5 and Virtex-6

R Anitha, V Bagyaveereswaran - International Conference on Web and …, 2011 - Springer
Abstract The developing an Application Specific Integrated Circuits (ASICs) will cost very
high, the circuits should be proved and then it would be optimized before implementation …

[PDF][PDF] Comparative study of Braun's multiplier using FPGA devices

R Anitha, V Bagyaveereswaran - Int. J. Eng. Sci. Tech, 2011 - academia.edu
The development cost for ASIC are high, algorithms should be verified and optimized before
implementation. To decrease computational delay and improve resource utilization …

[PDF][PDF] Low power pilpelined FIR filter with enhanced row bypassing multiplier

S Sridevi, A Chowdary - Int. J. Commun. Antenna Propag, 2011 - researchgate.net
This paper presents a low power FIR filter with enhanced row bypassing multipliers. Direct
form architecture with pipelined stage is chosen for implementation. The presence of power …

Low complexity architecture of linear periodically time varying filter based on a switching representation

S Sridevi, R Dhuli, K Saketh… - … National Conference on …, 2013 - ieeexplore.ieee.org
This paper presents a low complexity architecture for a linear periodically time varying
(LPTV) filter. This architecture is based on input switching representation of LPTV filters. This …

[PDF][PDF] Architectures and Methodologies for Reducing Power in Multipliers: A Literature Survey

M Bassi, P Kaur, A Singh - International Journal of Computer Applications, 2014 - Citeseer
Multiplier is the most basic unit of any electronic hardware whether it is microprocessor in
cell phone or any DSP's processors for signal processing. So power dissipation by multiplier …

[PDF][PDF] Performance Analysis of Different 8x8 Bit CMOS Multiplier using 65nm Technology

S Rani, A Kumar, V Singla, R Singla - International Journal of …, 2016 - researchgate.net
In this paper different low power 8x8 bit multipliers which are implemented with Tanner Tool
v13. 0 at 250MHz and 500MHz frequency with 65nm technology which is having a supply …

Low-Power and Area-Efficient Approximate Parallel Design Using Bypassing

NK Nandi, D AN - 2019 - papers.ssrn.com
Power and Area have always been topics of major concern in VLSI. Multipliers and adders
form the most vital units for a variety of DSP applications. Hence reducing the power …

[PDF][PDF] Year of Publication: 2016

P Rani - Research and Development, 2016 - kasturbagandhicollege.ac.in
Bacteria play a vital role in technology for the production of extracellular enzymes especially
proteases which are widely used on an industrial scale in many laundr industries. Soil …