Improving cache lifetime reliability at ultra-low voltages
Voltage scaling is one of the most effective mechanisms to reduce microprocessor power
consumption. However, the increased severity of manufacturing-induced parameter …
consumption. However, the increased severity of manufacturing-induced parameter …
An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 graphics DRAM with low power and low noise data bus inversion
4 Gb/s/pin 32 bit 512 Mb GDDR4 (Graphics Double Data Rate 4) SDRAM was implemented
by using an 80 nm CMOS process. It employs a data bus inversion (DBI) coding to overcome …
by using an 80 nm CMOS process. It employs a data bus inversion (DBI) coding to overcome …
FEXT-eliminated stub-alternated microstrip line for multi-gigabit/second parallel links
A stub-alternated microstrip line is proposed for multi-gigabit/second parallel links on a PCB.
Without guard traces, the uniformly distributed stub structure eliminates the far-end crosstalk …
Without guard traces, the uniformly distributed stub structure eliminates the far-end crosstalk …
Adaptive cache design to enable reliable low-voltage operation
The performance/energy trade-off is widely acknowledged as a primary design
consideration for modern processors. A less discussed, though equally important, trade-off is …
consideration for modern processors. A less discussed, though equally important, trade-off is …
A 60nm 6Gb/s/pin GDDR5 graphics DRAM with multifaceted clocking and ISI/SSN-reduction techniques
SJ Bae, YS Sohn, KI Park, KH Kim… - … Solid-State Circuits …, 2008 - ieeexplore.ieee.org
Demand for high-speed DRAM in graphics application pushes a single-ended I/O signaling
to operate up to 6Gb/s [1]. To maintain the speed increase, the GDDR5 specification shifts …
to operate up to 6Gb/s [1]. To maintain the speed increase, the GDDR5 specification shifts …
Data bus inversion apparatus, systems, and methods
T Hollis - US Patent 7,616,133, 2009 - Google Patents
BACKGROUND Data transmission between integrated circuit devices may take the form of
high-speed data signals, also called data bits, driven over parallel channels in a data bus …
high-speed data signals, also called data bits, driven over parallel channels in a data bus …
A 75 nm 7 Gb/s/pin 1 Gb GDDR5 graphics memory device with bandwidth improvement techniques
R Kho, D Boursin, M Brox, P Gregorius… - IEEE journal of solid …, 2009 - ieeexplore.ieee.org
Modern graphics subsystems (gaming PCs, midhigh end graphics cards, game consoles)
have reached the 2.6-2.8 Gb/s/pin regime with GDDR3/GDDR4, and experimental work has …
have reached the 2.6-2.8 Gb/s/pin regime with GDDR3/GDDR4, and experimental work has …
Data bus inversion apparatus, systems, and methods
T Hollis - US Patent 8,094,045, 2012 - Google Patents
Apparatus, Systems, and methods are disclosed Such as those that operate to encode data
bits transmitted on a plurality of channels according to at least one of multiple Data Bus Inver …
bits transmitted on a plurality of channels according to at least one of multiple Data Bus Inver …
Non-volatile storage device with adaptive data bus inversion
D Brief - US Patent 10,621,116, 2020 - Google Patents
An apparatus includes an inversion circuit configured to invert a data word, a first partial-
inversion circuit configured to invert a first portion of the data word, a second partial …
inversion circuit configured to invert a first portion of the data word, a second partial …
Unequal-error-protection codes in SRAMs for mobile multimedia applications
X Yang, K Mohanram - 2011 IEEE/ACM International …, 2011 - ieeexplore.ieee.org
In this paper, we introduce unequal-error-protection error correcting codes (UEPECCs) to
improve SRAM reliability at low supply voltages for mobile multimedia applications. The …
improve SRAM reliability at low supply voltages for mobile multimedia applications. The …