Circuit Design of 3-and 4-Bit Flash Analog-to-Digital Converters Based on Memristors

G Dai, X Du, W Xie, T Ni, M Han, D Wu - Electronics, 2023 - mdpi.com
Given its advantageous power-and area-efficiency characteristics and its compatibility with
traditional CMOS technology, the memristor has emerged as a promising candidate for low …

[图书][B] Developing digital RF memories and transceiver technologies for electromagnetic warfare

PE Pace - 2022 - books.google.com
This book provides a comprehensive resource and thorough treatment in the latest
development of Digital RF Memory (DRFM) technology and their key role in maintaining …

Design of low–power 4-bit Flash ADC using Multiplexer based encoder in 90nm CMOS process

DS Sam, P Sam Paul, DJ Jingle, PM Paul… - … Journal of Electronics …, 2022 - journals.pan.pl
This work describes a 4-bit Flash ADC with low power consumption. The performance
metrics of a Flash ADC depend on the kind of comparator and encoder used. Hence …

Design and analysis of a low-power high-speed charge-steering based StrongARM comparator

MM Ayesh, S Ibrahim… - 2016 28th International …, 2016 - ieeexplore.ieee.org
This paper presents an ultra low-power high-speed dynamic comparator. The proposed
dynamic comparator is designed and simulated in a 65-nm CMOS technology. It dissipates 7 …

ADC-Less Reprogrammable RRAM Array Architecture for In-Memory Computing

A Dongre, B Boro, G Trivedi - IEEE Transactions on Very Large …, 2023 - ieeexplore.ieee.org
Nonvolatile memories, such as resistive random access memory (RRAM), for in-memory
computing (IMC), have shown great potential in accelerating neural networks (NNs) …

A 4 bit quantum voltage comparator based flash ADC for low noise applications

T Kalita, B Das - 2016 Conference on Emerging Devices and …, 2016 - ieeexplore.ieee.org
Analog to Digital Converter (ADC) is an essential part of a mixed signal circuit design, which
acts as a bridge between naturally occurring analog signals and digital signals. It has been …

A 24-mW 65-nm CMOS TI-flash ADC for multi-standard serial-link receivers

KA El-Gammal, SA Ibrahim - 2016 IEEE 59th International …, 2016 - ieeexplore.ieee.org
A 4-channel 4-bit flash analog-to-digital converter is presented with 10Gbps sampling speed
and a figure-of-merit of 182 fJ/conversion-step. It uses a conventional clocking scheme …

A low-power high-speed charge-steering comparator for high-speed applications

AH Hassan, MM Aboudina… - 2016 14th IEEE …, 2016 - ieeexplore.ieee.org
Comparators are essential blocks in implementing high speed flash ADCs. This paper
introduces a low-power high-speed charge-steering comparator with off-chip clock …

A low power offset voltage calibration method for flash ADCs

S Chatterjee, S Roy - Integration, 2023 - Elsevier
In this manuscript, a lookup table (LUT) based offset voltage cancellation algorithm has
been presented. The proposed algorithm helps to mitigate the ADC output non-linearity due …

Design of a 14-Bit 1 MS/s Successive Approximation Analog-to-Digital Converter

Q Li, X Cao, L Wang, M Song - Journal of Power and Energy Engineering, 2024 - scirp.org
A 14-bit successive approximation analog-to-digital converter (SAR ADC) with capacitive
calibration has been designed based on the SMIC. 18 μm CMOS process. The overall …