A 1.1-V 6.4-Gb/s/pin 16-Gbit DDR5 is presented in 10-nm class CMOS technology. Various
functions and circuits' techniques are newly adopted to improve performance and power …

This brief presents a fast-locking multiphase closed-loop delay-locked loop (DLL). The
proposed DLL employs a novel rapid-tracking time-to-digital converter that spends only two …

As data transfer rates increase, clock frequencies used for high-speed data paths also
increase. Thus, multiphase clocks are typically utilized in DRAMs to relax timing margins …

A fast-locking all-digital delay-locked loop (DLL) with closed-loop duty-cycle correction
(DCC) capability is proposed for clock synchronization in DRAM. A new cyclic-locking loop …

In an effort to keep pace with bandwidth growth, DRAM employes the quad data rate (QDR)
to transfer four data in one clock cycle. In recent graphic memories, QDR is being …

A 3 MHz-to-1.8 GHz, 94 μW-to-9.5 mW, all-digital delay-locked loop (ADDLL) using 65-nm
CMOS technology is presented. In this paper, a cyclic half-delay-line architecture that uses …

In this paper, delay-locked loops (DLLs) used in dynamic random access memory (DRAM)
are analyzed. DLLs can be categorized into digital-or analog-based topologies. This …

This paper proposes a 90° phase-shift delay-locked loop (DLL) used in dynamic RAM for
data sampling clock generation. The proposed DLL alleviates process variation issues …

This brief presents a phase rotator (PR)-based delay-locked loop (DLL) for a dynamic
random-access memory interface in 28-nm CMOS technology. A direct input–output …

In this paper, a quadrature error corrector (QEC) for next generation DRAM interface is
proposed. The proposed QEC corrects duty-cycle error and 4-phase skew simultaneously …