A survey on energy-efficient methodologies and architectures of network-on-chip
Integration of large number of electronic components on a single chip has resulted in
complete and complex systems on a single chip. The energy efficiency in the System-on …
complete and complex systems on a single chip. The energy efficiency in the System-on …
A case study on NoC router architecture for optimizing the latency
S Ramani, J Sundararajan - 2013 International Conference on …, 2013 - ieeexplore.ieee.org
With the growing research, the Network on chip (NoC) architecture provides an opportunity
for high scalability and freedom from the limitations of complex wiring. In this paper, a survey …
for high scalability and freedom from the limitations of complex wiring. In this paper, a survey …
[HTML][HTML] Design of Efficient Router with Low Power and Low Latency for Network on Chip
M Deivakani, D Shanthi - Circuits and Systems, 2016 - scirp.org
The NoC consists of processing element (PE), network interface (NI) and router. This paper
proposes a hybrid scheme for Netwok of Chip (NoC), which aims at obtaining low latency …
proposes a hybrid scheme for Netwok of Chip (NoC), which aims at obtaining low latency …
[PDF][PDF] TRAFFIC PATTERNS ANALYSIS IN HYBRID NOC DESIGN
M DEIVAKANI, PB DEVI, J BOOMA - researchgate.net
The power consumption and other crucial parameters analysis is important for the design of
efficient and high performance router architecture for wired or wireless communications. The …
efficient and high performance router architecture for wired or wireless communications. The …
Comparative Study of Topologies in 3D NoC
Networks on Chip is a communication subsystem on an integrated circuit (commonly known
as” chip”). As the number of cores and IP blocks integrated on a single chip are increasing …
as” chip”). As the number of cores and IP blocks integrated on a single chip are increasing …