Thread-Level Speculation (TLS) is a promising technique that allows the parallel execution
of sequential code without relying on a prior, compile-time-dependence analysis. In this …

The introduction of hardware transactional memory (HTM) into commercial processors
opens a door for designing and implementing scalable synchronization mechanisms. One …

The ubiquity of multicore processors has led programmers to write parallel and concurrent
applications to take advantage of the underlying hardware and speed up their executions. In …

Detecting data races is important for debugging shared-memory multithreaded programs,
but the high runtime overhead prevents the wide use of dynamic data race detectors. This …

Hardware Lock Elision (HLE) represents a promising technique to enhance parallelism of
concurrent applications relying on conventional, lock-based synchronization. The idea at the …

Transactional lock elision (TLE) is a well-known technique that exploits hardware
transactional memory (HTM) to introduce concurrency into lock-based software. It achieves …

Wireless Sensor Networks (WSNs) are playing remarkable contribution in real time decision
making by actuating the surroundings of environment. As a consequence, the contemporary …

The notion of a universal construction is central in computing science: the wheel has not to
be reinvented for each new problem. In the context of n-process asynchronous distributed …

In this paper, a system is presented which implements transactions migration to an
asymmetric multiprocessor in order to decrease the probability of conflicts and improve …

Locks have been widely used as an effective synchronization mechanism among processes
and threads. However, we observe that a large number of false inter-thread dependencies …