System-on-Chip (SoC) complexity and the increasing costs of silicon motivate the breaking of an SoC into smaller" chiplets." A chiplet-based SoC design process has the promise to …
Aggressive transistor scaling continues to drive increasingly complex digital designs. The large number of transistors available today enables the development of chip multiprocessors …
A Mejia, J Flich, J Duato, SA Reinemo… - … 20th IEEE International …, 2006 - ieeexplore.ieee.org
Computers get faster every year, but the demand for computing resources seems to grow at an even faster rate. Depending on the problem domain, this demand for more power can be …
J Flich, T Skeie, A Mejia, O Lysne… - … on Parallel and …, 2011 - ieeexplore.ieee.org
Most standard cluster interconnect technologies are flexible with respect to network topology. This has spawned a substantial amount of research on topology-agnostic routing …
Extreme transistor technology scaling is causing increasing concerns in device reliability: the expected lifetime of individual transistors in complex chips is quickly decreasing, and the …
A Mejia, M Palesi, J Flich, S Kumar… - … Transactions on Very …, 2009 - ieeexplore.ieee.org
An efficient routing algorithm is important for large on-chip networks [network-on-chip (NoC)] to provide the required communication performance to applications. Implementing NoC …
Psychoacoustic studies show that human listeners are sensitive to speaking rate variations. Automatic speech recognition (ASR) systems are even more affected by the changes in rate …
Lossless interconnection networks are omnipresent in high performance computing systems, data centers and network-on-chip architectures. Such networks require efficient …
A Jouraku, M Koibuchi, H Amano - IEEE Transactions on …, 2007 - ieeexplore.ieee.org
System area networks (SANs), which usually accept arbitrary topologies, have been used to connect hosts in PC clusters. Although deadlock-free routing is often employed for low …