This thesis explores the design and architecture of a balanced ternary RISC-V-like Energy efficient Balanced tErnary Logic (REBEL)-2 Central Processing Unit (CPU). There is a …
S Bos, JB Nilsen, H Gundersen - 2020 IEEE 8th Electronics …, 2020 - ieeexplore.ieee.org
This paper presents a method to read and write ternary (three-valued) signals on memristors to control a robotic actuator in real-time. The paper is a continuation of earlier work by [1] …
Ternary logic theory and CNTFETs The basic theory of ternary logic and CNTFETs are explored and explained, to set a theoretical context and build a base for the rest of the …
Ternary logic, in which the number of discrete logic levels are restricted to three, has been a subject to excessive research over several years. In this position paper we discuss …
This thesis presents two circuits capable of writing ternary data to a memristor, and reading that data without corrupting it. It also investigated how the mean metastable switch memristor …