Survey of scheduling techniques for addressing shared resources in multicore processors
S Zhuravlev, JC Saez, S Blagodurov… - ACM Computing …, 2012 - dl.acm.org
Chip multicore processors (CMPs) have emerged as the dominant architecture choice for
modern computing platforms and will most likely continue to be dominant well into the …
modern computing platforms and will most likely continue to be dominant well into the …
Simba: Scaling deep-learning inference with multi-chip-module-based architecture
Package-level integration using multi-chip-modules (MCMs) is a promising approach for
building large-scale systems. Compared to a large monolithic die, an MCM combines many …
building large-scale systems. Compared to a large monolithic die, an MCM combines many …
A survey of techniques for cache partitioning in multicore processors
S Mittal - ACM Computing Surveys (CSUR), 2017 - dl.acm.org
As the number of on-chip cores and memory demands of applications increase, judicious
management of cache resources has become not merely attractive but imperative. Cache …
management of cache resources has become not merely attractive but imperative. Cache …
CPI2 CPU performance isolation for shared compute clusters
X Zhang, E Tune, R Hagmann, R Jnagal… - Proceedings of the 8th …, 2013 - dl.acm.org
Performance isolation is a key challenge in cloud computing. Unfortunately, Linux has few
defenses against performance interference in shared resources such as processor caches …
defenses against performance interference in shared resources such as processor caches …
Cuanta: quantifying effects of shared on-chip resource interference for consolidated virtual machines
Workload consolidation is very attractive for cloud platforms due to several reasons
including reduced infrastructure costs, lower energy consumption, and ease of …
including reduced infrastructure costs, lower energy consumption, and ease of …
Micro-pages: increasing DRAM efficiency with locality-aware data placement
Power consumption and DRAM latencies are serious concerns in modern chip-
multiprocessor (CMP or multi-core) based compute systems. The management of the DRAM …
multiprocessor (CMP or multi-core) based compute systems. The management of the DRAM …
Simple but effective heterogeneous main memory with on-chip memory controller support
System-in-Package (SiP) and 3D integration are promising technologies to bring more
memory onto a microprocessor package to mitigate the" memory wall" problem. In this …
memory onto a microprocessor package to mitigate the" memory wall" problem. In this …
Handling the problems and opportunities posed by multiple on-chip memory controllers
Modern processors such as Tilera's Tile64, Intel's Nehalem, and AMD's Opteron are
migrating memory controllers (MCs) on-chip, while maintaining a large, flat memory address …
migrating memory controllers (MCs) on-chip, while maintaining a large, flat memory address …
Jenga: Software-defined cache hierarchies
Caches are traditionally organized as a rigid hierarchy, with multiple levels of progressively
larger and slower memories. Hierarchy allows a simple, fixed design to benefit a wide range …
larger and slower memories. Hierarchy allows a simple, fixed design to benefit a wide range …
Whirlpool: Improving dynamic cache management with static data classification
Cache hierarchies are increasingly non-uniform and difficult to manage. Several techniques,
such as scratchpads or reuse hints, use static information about how programs access data …
such as scratchpads or reuse hints, use static information about how programs access data …