The widespread proliferation of the Chip Multi-Processor (CMP) paradigm has cemented the
criticality of the on-chip interconnection fabric. The Network-on-Chip (NoC) is becoming …

In this survey, we address the concept of network in three different contexts representing the
deterministic, probabilistic, and statistical physics-inspired design paradigms. More …

As silicon technology scales, modern processors and embedded systems are rapidly shifting
towards complex chip multi-processor (CMP) and system-on-chip (SoC) designs, comprising …

A formal modeling of a Network-on-Chip (NoC) using a communicating finite state machine
(CFSM) is presented in this article. We have automated the CFSM model generation for …

The current technology allows the integration on a single die of complex systems-on-chip
(SoCs) that are composed of manufactured blocks (IPs), interconnected through specialized …

Networks-on-Chip (NoC) are becoming increasingly susceptible to emerging reliability
threats. The need to detect and localize the occurrence of faults at runtime is steadily …

Network on chip (NoC) has surfaced as a crucial interconnection strategy in modern digital
systems, thereby demanding meticulous verification. Due to its multiple nodes and high …

This paper presents a formal model and a systematic approach to the validation of
communication architectures at a high level of abstraction. This model is described …

Network on chip (NoC) is a system design methodology that uses on-chip routers for
integrating the resources on a system on chip (SoC). Applications on the SoC communicate …

COSI: A Framework for the Design of Interconnection Networks Page 1 COSI: A Framework for
the Design of Interconnection Networks Alessandro Pinto University of California, Berkeley Luca …