In this paper, a fully-synthesizable digital-to-time (DTC)-based fractional-Nmultiplying delay-
locked loop (MDLL) is presented. Noise and linearity of synthesizable DTCs are analyzed …

In this work, we present an open-source fully-synthesizable fractional-N all-digital phase-
locked loop (ADPLL) designed for a Bluetooth low-energy (BLE) transmitter (TX) along with …

In this paper, we propose a novel standard-cell-based OTA architecture based on an
improved version of the differential to single-ended converter, previously proposed by the …

This article presents an injection-locked (IL) ring-oscillator-based fractional-digital phase
locked loop (DPLL) supporting Bluetooth low energy (BLE) frequency modulation with an …

A standard-cell-based fractional-N synthesizable phase-locked loop (PLL)[or multiplying-
delay-locked loop (MDLL)] is proposed, where the multiple phases of the three-stage ring …

This article presents a 915-MHz ultra-low-power (ULP) sub-sampling phase-tracking
receiver (SSPT-RX). It is targeted for the power-constrained devices that need short range …

Phase-locked loops (PLLs) are crucial building blocks in almost everry electronic device.
With the continuous scaling down of CMOS process, conventional custom-designed PLLs …

This paper describes a low-power IoT sensor node SoC that can be used for factory
automation and wearable healthcare applications. It features dynamic power scheduling …

As semiconductor fabrication process become complex to achieve target yield and
performance in sub-20nm field-effect transistors (FETs), not only the number of design rule …

This paper presents a fully integrated yet compact receiver front-end for Sub-GHz
applications such as Internet-of-Things (IoT). The low noise amplifier (LNA) matching …