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US8418023B2 - Low density parity check decoder for irregular LDPC codes - Google Patents
US8418023B2 - Low density parity check decoder for irregular LDPC codes - Google Patents …

In one embodiment, a forward substitution component performs forward substitution based
on a lower-triangular matrix and an input vector to generate an output vector. The forward …

A nonvolatile memory system, a nonvolatile memory controller and a method for reducing
latency of a memory controller are disclosed. Upon the occurrence of one or more of an …

Embodiments of the present invention are methods for break ing one or more trapping sets
in a near codeword of a failed graph-based decoder, eg, an LDPC decoder. The methods …

Abstract A Solid State Drive (SSD) that includes a host connector receptacle for connecting
to a host computer, a plurality of NAND devices and a nonvolatile memory controller. The …

A method for reusing a destination block related to garbage collection (GC) in a memory
device, the associated memory device and the controller thereof, and the associated …

See application file for complete search history. In one embodiment, an LDPC
decoderperforms a targeted bit adjustment method to recover a valid codeword after the …

In one embodiment, a turbo equalizer is selectively operable in either first or second modes.
In the first mode, layered (low-density parity-check (LDPC)) decoding is performed on soft …

A nonvolatile memory controller and a method for erase suspend management are
disclosed. The nonvolatile memory controller includes an erase suspend circuit configured …