[PDF][PDF] Patterns for quantum error handling

M Beisel, J Barzen, F Leymann, F Truger… - Proceedings of the …, 2022 - iaas.uni-stuttgart.de
The capabilities of current quantum computers are limited by their high error rates. Thus,
reducing the impact of these errors is one of the crucial challenges for the successful …

Ice: An intelligent cognition engine with 3d nand-based in-memory computing for vector similarity search acceleration

HW Hu, WC Wang, YH Chang, YC Lee… - 2022 55th IEEE/ACM …, 2022 - ieeexplore.ieee.org
Vector similarity search (VSS) for unstructured vectors generated via machine learning
methods is a promising solution for many applications, such as face search. With increasing …

Soft decision decoding with cyclic information set and the decoder architecture for cyclic codes

W Chen, T Zhao, C Han - Electronics, 2023 - mdpi.com
The soft decision decoding algorithm for cyclic codes, especially the maximum likelihood
(ML) decoding algorithm, can obtain significant performance superior to that of algebraic …

A universal, low-delay, SEC-DEC-TAEC code for state register protection

M Dong, W Pan, Z Qiu, X Qi, L Zheng, H Liu - IEEE Access, 2022 - ieeexplore.ieee.org
Finite State Machine (FSM) is widely used in electronic systems and its reliability is critical to
the system. Ionizing radiation induced soft error is one of the major concerns in the design of …

Enhancing Data Storage Reliability and Error Correction in Multilevel NOR and NAND Flash Memories through Optimal Design of BCH Codes

S Nabipour, J Javidan - arXiv preprint arXiv:2307.08084, 2023 - arxiv.org
The size reduction of transistors in the latest flash memory generation has resulted in
programming and data erasure issues within these designs. Consequently, ensuring …

A Hybrid Technique based on ECC and Hardened Cells for Tolerating Random Multiple-Bit Upsets in SRAM arrays

D Gil-Tomás, LJ Saiz-Adalid, J Gracia-Morán… - IEEE …, 2024 - ieeexplore.ieee.org
MBU is an increasing challenge in SRAM memory, due to the chip's large area of SRAM,
and supply power scaling applied to reduce static consumption. Powerful ECCs can cope …

Gradient Descent Iterative Correction Unit for Fixed Point Parity Based Codes

O Boncalo, A Amaricai - … on Defect and Fault Tolerance in VLSI …, 2023 - ieeexplore.ieee.org
This paper proposes a novel iterative decoding method-Gradient Descent Symbol Update-
for real number parity based error correction codes, as well as its corresponding hardware …

A Proposal of an ECC-based Adaptive Fault-Tolerant Mechanism for 16-bit data words

J Gracia-Morán, LJ Saiz-Adalid… - IEEE Latin America …, 2024 - ieeexplore.ieee.org
With the integration scale level reached in CMOS technology, memory systems provide a
great storage capacity, but at the price of an augment in their fault rate. In this way, the …

Zero-Space In-Weight and In-Bias Protection for Floating-Point-based CNNs

JC Ruiz, D de Andrés, LJ Saiz-Adalid… - 2024 19th European …, 2024 - ieeexplore.ieee.org
Deploying convolutional neural networks (CNNs) in image classification systems requires
balancing conflicting goals, like throughput, power consumption, and silicon area. In safety …

Design, implementation and evaluation of a low redundant error correction code

J Gracia-Morán, LJS Adalid, JCB Calvo… - IEEE Latin America …, 2021 - ieeexplore.ieee.org
The continuous raise in the integration scale of CMOS technology has provoked an augment
in the fault rate. Particularly, computer memory is affected by Single Cell Upsets (SCU) and …