Recent trends in novel semiconductor devices
A Pandey - Silicon, 2022 - Springer
The VLSI industry has grown a lot for several decades. The Packing density of integrated
circuits has been increased without compromising the functionality. Scaling of …
circuits has been increased without compromising the functionality. Scaling of …
Insight into gate-induced drain leakage in silicon nanowire transistors
J Fan, M Li, X Xu, Y Yang, H Xuan… - IEEE Transactions on …, 2014 - ieeexplore.ieee.org
In this paper, detailed physical mechanisms of gate-induced drain leakage (GIDL) in gate-all-
around silicon nanowire transistors (SNWTs) are investigated and verified by experiments …
around silicon nanowire transistors (SNWTs) are investigated and verified by experiments …
Challenges of 22 nm and beyond CMOS technology
R Huang, HM Wu, JF Kang, DY Xiao, XL Shi… - Science in China Series …, 2009 - Springer
It is predicted that CMOS technology will probably enter into 22 nm node around 2012.
Scaling of CMOS logic technology from 32 to 22 nm node meets more critical issues and …
Scaling of CMOS logic technology from 32 to 22 nm node meets more critical issues and …
Simulations of Statistical Variability in n-Type FinFET, Nanowire, and Nanosheet FETs
Four sources of variability, metal grain granularity (MGG), line-edge roughness (LER), gate-
edge roughness (GER), and random discrete dopants (RDD), affecting the performance of …
edge roughness (GER), and random discrete dopants (RDD), affecting the performance of …
Scaling of nanowire transistors
This paper considers the scaling of nanowire transistors to 10-nm gate lengths and below.
The 2-D scale length theory for a cylindrical surrounding-gate MOSFET is reviewed first …
The 2-D scale length theory for a cylindrical surrounding-gate MOSFET is reviewed first …
First experimental demonstration of gate-all-around III–V MOSFETs by top-down approach
The first inversion-mode gate-all-around (GAA) III-V MOSFETs are experimentally
demonstrated with a high mobility In 0.53 Ga 0.47 As channel and atomic-layer-deposited …
demonstrated with a high mobility In 0.53 Ga 0.47 As channel and atomic-layer-deposited …
Ultimate vertical gate-all-around metal–oxide–semiconductor field-effect transistor and its three-dimensional integrated circuits
S Ye, K Yamabe, T Endoh - Materials Science in Semiconductor Processing, 2021 - Elsevier
Abstract According to the International Roadmap for Devices and Systems, gate-all-around
(GAA) metal–oxide–semiconductor field-effect transistors (MOSFETs) will become the main …
(GAA) metal–oxide–semiconductor field-effect transistors (MOSFETs) will become the main …
Investigations on line-edge roughness (LER) and line-width roughness (LWR) in nanoscale CMOS technology: Part II–experimental results and impacts on device …
In the part I of this paper, the correlation between line-edge roughness (LER) and line-width
roughness (LWR) is investigated by theoretical modeling and simulation. In this paper …
roughness (LWR) is investigated by theoretical modeling and simulation. In this paper …
Predictive 3-D modeling of parasitic gate capacitance in gate-all-around cylindrical silicon nanowire MOSFETs
In this paper, an analytical model for parasitic gate capacitances in gate-all-around
cylindrical silicon nanowire MOSFETs (SNWTs) is developed for the first time. A practical 3 …
cylindrical silicon nanowire MOSFETs (SNWTs) is developed for the first time. A practical 3 …
Nanowire FET and finFET hybrid technology
The present invention provides hybrid nanowire field effect transistor (FET) and FinFET
devices and methods for fabri cation thereof. In one aspect of the invention, a method for …
devices and methods for fabri cation thereof. In one aspect of the invention, a method for …