Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits
K Roy, S Mukhopadhyay… - Proceedings of the …, 2003 - ieeexplore.ieee.org
High leakage current in deep-submicrometer regimes is becoming a significant contributor
to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide …
to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide …
Research progress on porous low dielectric constant materials
M Xie, M Li, Q Sun, W Fan, S Xia, W Fu - Materials Science in …, 2022 - Elsevier
With the rapid development of ultra-large-scale integration (ULSI) of integrated circuits, the
feature size of the silicon chip continues shrinking and the physical gate length is …
feature size of the silicon chip continues shrinking and the physical gate length is …
Scaling aligned carbon nanotube transistors to a sub-10 nm node
Aligned semiconducting carbon nanotubes are a potential alternative to silicon in the
creation of scaled field-effect transistors (FETs) due to their easy miniaturization and high …
creation of scaled field-effect transistors (FETs) due to their easy miniaturization and high …
Radiofrequency transistors based on aligned carbon nanotube arrays
The development of next-generation wireless communication technology requires integrated
radiofrequency devices capable of operating at frequencies greater than 90 GHz. Carbon …
radiofrequency devices capable of operating at frequencies greater than 90 GHz. Carbon …
New generation of predictive technology model for sub-45 nm early design exploration
A predictive MOSFET model is critical for early circuit design research. To accurately predict
the characteristics of nanoscale CMOS, emerging physical effects, such as process …
the characteristics of nanoscale CMOS, emerging physical effects, such as process …
Complementary transistors based on aligned semiconducting carbon nanotube arrays
High-density semiconducting aligned carbon nanotube (A-CNT) arrays have been
demonstrated with wafer-scale preparation of materials and have shown high performance …
demonstrated with wafer-scale preparation of materials and have shown high performance …
High-performance interconnects: An integration overview
RH Havemann, JA Hutchby - Proceedings of the IEEE, 2001 - ieeexplore.ieee.org
The Information Revolution and enabling era of silicon ultralarge-scale integration (ULSI)
have spawned an ever-increasing level of functional integration on-chip, driving a need for …
have spawned an ever-increasing level of functional integration on-chip, driving a need for …
Scaling of stack effect and its application for leakage reduction
S Narendra, V De, D Antoniadis… - Proceedings of the …, 2001 - dl.acm.org
Technology scaling demands a decrease in both Vdd and Vt to sustain historical delay
reduction, while restraining active power dissipation. Scaling of Vt however leads to …
reduction, while restraining active power dissipation. Scaling of Vt however leads to …
[图书][B] System-on-chip test architectures: nanometer design for testability
LT Wang, CE Stroud, NA Touba - 2010 - books.google.com
Modern electronics testing has a legacy of more than 40 years. The introduction of new
technologies, especially nanometer technologies with 90nm or smaller geometry, has …
technologies, especially nanometer technologies with 90nm or smaller geometry, has …
Extension and source/drain design for high-performance FinFET devices
J Kedzierski, M Ieong, E Nowak… - … on Electron Devices, 2003 - ieeexplore.ieee.org
Double gate devices based upon the FinFET architecture are fabricated, with gate lengths
as small as 30 nm. Particular attention is given to minimizing the parasitic series resistance …
as small as 30 nm. Particular attention is given to minimizing the parasitic series resistance …