An output buffer circuit may include a pulse generator, a transmitter, and an emphasis
controller. The pulse generator generates a pulse signal for determining an emphasis …

A semiconductor memory device is effectively able to adjust operation time for on-die
termination (ODT). The semiconductor memory device includes a latency control unit, a …

(57) ABSTRACT A power supply control circuit includes a poWer supply con trol unit con?
gured to receive a rank mode signal and gener ate a plurality of poWer supply enable …

BACKGROUND Memory controllers communicate signals containing data, addresses or
commands, to one or more memory devices through signal lines. For the command/address …

In one embodiment of the present invention, a semi conductor apparatus having a plurality
of semiconductor chips is configured in Such a manner that the plurality of semiconductor …

(57) ABSTRACT A semiconductor circuit apparatus having a commonly shared control unit
that coordinates reading and writing timed activities in two ranked subcircuits is presented …

A high-speed bus interface with an adaptive swing driver. A high speed interface includes a
transmitter and a receiver coupled via a bus. The transmitter has an adaptive swing driver …

The present invention relates generally to an electronic circuit and, more particularly, to an
output driver for effi ciently transmitting data to a reception system. 2. Description of the …

SUMMARY A data driver that can reduce driving hindering elements and improve a data
input/output speed is disclosed herein. In one embodiment, a data driver includes a …

Eyal application No. 61/099,646, filed on Sep. Embodiments of a memory controller are
described. This s memory controller communicates signals to a memory device (51) Int. Cl …