Review of progress in calculation and simulation of high-temperature oxidation

D Gao, Z Shen, K Chen, X Zhou, H Liu, J Wang… - Progress in Materials …, 2024 - Elsevier
High-temperature oxidation can precipitate chemical and mechanical degradations in
materials, potentially leading to catastrophic failures. Thus, understanding the mechanisms …

Investigations on line-edge roughness (LER) and line-width roughness (LWR) in nanoscale CMOS technology: Part II–experimental results and impacts on device …

R Wang, X Jiang, T Yu, J Fan, J Chen… - IEEE transactions on …, 2013 - ieeexplore.ieee.org
In the part I of this paper, the correlation between line-edge roughness (LER) and line-width
roughness (LWR) is investigated by theoretical modeling and simulation. In this paper …

[HTML][HTML] Two-dimensional modeling of the self-limiting oxidation in silicon and tungsten nanowires

M Liu, P Jin, Z Xu, DAH Hanaor, Y Gan… - Theoretical and Applied …, 2016 - Elsevier
Self-limiting oxidation of nanowires has been previously described as a reaction-or diffusion-
controlled process. In this letter, the concept of finite reactive region is introduced into a …

Gated Si-tip with on-tip integrated gate-all-around field effect transistor for actively controlled field electron emission

M Zeng, Y Huang, Y Huang, J Chen… - IEEE Electron Device …, 2022 - ieeexplore.ieee.org
Gated Si-tip with on-tip integrated gate-all-around field effect transistor using hyperbolic
nano-channel (Hy-GAAFET) for actively controlled field electron emission is presented. Fully …

[HTML][HTML] Precise fabrication of uniform sub-10-nm-diameter cylindrical silicon nanopillars via oxidation control

S Ye, K Yamabe, T Endoh - Scripta Materialia, 2021 - Elsevier
Abstract Silicon (Si) nanopillar (NP)-based gate-all-around metal–oxide–semiconductor field-
effect transistors (MOSFETs) are considered the primary components of next-generation …

Oxidation of silicon nanopillars

S Ye, K Yamabe, T Endoh - The Journal of Physical Chemistry C, 2021 - ACS Publications
Systematic investigation of dry oxidation of sub-100 nm diameter Si nanopillars (NPs) of
various diameters under varying conditions reveals that at 900° C, the oxidation involves a …

[HTML][HTML] TCAD modeling and simulation of self-limiting oxide growth and boron segregation during vertical silicon nanowire processing

C Rossi, J Müller, P Pichler, PP Michałowski… - Materials Science in …, 2024 - Elsevier
Thermal oxidation is a key step for the fabrication of vertical gate-all-around nanowire field-
effect transistors (GAA-NW-FETs). It is used after the etching of nanopillars from the silicon …

Oxidation-induced stress in Si nanopillars

S Ye, K Yamabe, T Endoh - Journal of Materials Science, 2019 - Springer
In this work, we investigate the microstructure and oxidation of Si nanopillars and report that
the oxidation at the sidewall of Si pillars is initially retarded (the so-called self-limiting) and …

Non-uniaxial stress-assisted fabrication of nanoconstriction on vertical nanostructured Si

M Zeng, X Li, Y Huang, Z Huang, R Zhan… - …, 2019 - iopscience.iop.org
Vertically aligned Si nanoconstrictions have potential for applications of electronic, photonic
and phononic nanodevices. Herein, we report a featured method by utilizing the non …

Gate-all-around silicon nanowire transistor technology

R Huang, R Wang, M Li - Women in Microelectronics, 2020 - Springer
As a promising alternative to the fundamental device structure, the gate-all-around silicon
nanowire transistor (GAA SNWT) has been studied extensively for decades. In this chapter …