Design and Process Variation Analysis of High-performance n and p-channel Insulated-gate Asymmetric-DG MOSFET

N Mendiratta, SL Tripathi, MS Adhikari - Silicon, 2023 - Springer
Transistor miniaturization and reduction in power consumptions, are major driving factor for
designing the nanoscale transistor. But the impact of process variation on device …

A novel high-performance trench lateral double-diffused MOSFET with buried oxide bump layer

H Jia, Y Shen, H Wang, X Wang, Y Zhang, S Zhu… - Microelectronics …, 2023 - Elsevier
A shallow-trenched Lateral Double-Diffused MOSFET with folded drift region (FD LDMOS) is
proposed in this paper. The new structure divides the drift region into two parts. The left side …

Performance Comparison of 15-Level Multilevel Inverter Topologies

G Anusha, K Arora, H Sharma, SP Thota… - 2023 15th …, 2023 - ieeexplore.ieee.org
Multilevel inverters (MLI) have gained a significant emphasis in the area of renewable
energy applications in recent years. The popularity of MLIs is due to their ability to efficiently …

The Influence of Special Environments on SiC MOSFETs

Z Li, J Jiang, Z He, S Hu, Y Shi, Z Zhao, Y He, Y Chen… - Materials, 2023 - mdpi.com
In this work, the influences of special environments (hydrogen gas and high temperature,
high humidity environments) on the performance of three types of SiC MOSFETs are …

4H-SiC layer with multiple trenches in lateral double-diffused metal-oxide-semiconductor transistors for high temperature and high voltage applications

A Sohrabi-Movahed, AA Orouji - … of Vacuum Science & Technology B, 2023 - pubs.aip.org
In this paper, we present a novel lateral double-diffused metal-oxide-semiconductor
(LDMOS) transistor for high-temperature and high breakdown voltage applications. The key …

Design of a Configurable Third-Order - Filter Using QFG and BD-QFG MOS-Based OTA for Fast Locking Speed PLL

P Gupta, SK Jana - Journal of Circuits, Systems and Computers, 2023 - World Scientific
High-speed PLL is highly demanding with the advancement in the VLSI market. PLL
performance gets affected due to bandwidth limitation. This paper presents third-order …

Investigating Viability of Split-Stepped Gate Field Plate Design on Ga2O3 MOSFET for High Power Applications

P Goyal, H Kaur - Journal of Electronic Materials, 2024 - Springer
A split-stepped gate field plate design has been incorporated on a gallium oxide (Ga2O3)
metal-oxide semiconductor field-effect transistor (MOSFET). The aim of the present work is to …

Novel dynamic back-gate control technology for performance improvement in ultrathin double SOI LDMOS

M Li, A Liu, J Yao, J Zhang, Z Wang, F Liu… - Journal of Power …, 2024 - Springer
Novel performance improvement technology is developed for an ultrathin Double Silicon-on-
Insulator (DSOI) Lateral Double-diffused Metal–Oxide–Semiconductor (LDMOS) with a …

Optimization of 14 nm double gate Bi-GFET for lower leakage current

NHNM Nizam, AMA Hamid… - TELKOMNIKA …, 2023 - telkomnika.uad.ac.id
In recent years, breakthroughs in electronics technology have resulted in upgrades in the
physical properties of the metal oxide semiconductor field effect transistor (MOSFET) toward …

Study of silicon material MOS with low threshold potential

MS Adhikari, YK Verma, S Suman - AIP Conference Proceedings, 2023 - pubs.aip.org
In this paper, some changes carried out in the LDMOS known as MOSFET1 by utilizing
trench known as MOSFET2. In the proposed device silicon material acts as channel material …