Understanding reduced-voltage operation in modern DRAM devices: Experimental characterization, analysis, and mechanisms

KK Chang, AG Yağlıkçı, S Ghose, A Agrawal… - Proceedings of the …, 2017 - dl.acm.org
The energy consumption of DRAM is a critical concern in modern computing systems.
Improvements in manufacturing process technology have allowed DRAM vendors to lower …

Use ECP, not ECC, for hard failures in resistive memories

S Schechter, GH Loh, K Strauss, D Burger - ACM SIGARCH Computer …, 2010 - dl.acm.org
As leakage and other charge storage limitations begin to impair the scalability of DRAM, non-
volatile resistive memories are being developed as a potential replacement. Unfortunately …

ArchShield: Architectural framework for assisting DRAM scaling by tolerating high error rates

PJ Nair, DH Kim, MK Qureshi - ACM SIGARCH Computer Architecture …, 2013 - dl.acm.org
DRAM scaling has been the prime driver for increasing the capacity of main memory system
over the past three decades. Unfortunately, scaling DRAM to smaller technology nodes has …

Thread motion: fine-grained power management for multi-core systems

KK Rangan, GY Wei, D Brooks - ACM SIGARCH Computer Architecture …, 2009 - dl.acm.org
Dynamic voltage and frequency scaling (DVFS) is a commonly-used power-management
scheme that dynamically adjusts power and performance to the time-varying needs of …

Ultralow-voltage process-variation-tolerant Schmitt-trigger-based SRAM design

JP Kulkarni, K Roy - IEEE transactions on very large scale …, 2011 - ieeexplore.ieee.org
We analyze Schmitt-Trigger (ST)-based differential-sensing static random access memory
(SRAM) bitcells for ultralow-voltage operation. The ST-based SRAM bitcells address the …

Reducing cache power with low-cost, multi-bit error-correcting codes

C Wilkerson, AR Alameldeen, Z Chishti, W Wu… - Proceedings of the 37th …, 2010 - dl.acm.org
Technology advancements have enabled the integration of large on-die embedded DRAM
(eDRAM) caches. eDRAM is significantly denser than traditional SRAMs, but must be …

FREE-p: Protecting non-volatile memory against both hard and soft errors

DH Yoon, N Muralimanohar, J Chang… - 2011 IEEE 17th …, 2011 - ieeexplore.ieee.org
Emerging non-volatile memories such as phase-change RAM (PCRAM) offer significant
advantages but suffer from write endurance problems. However, prior solutions are oblivious …

ERSA: Error resilient system architecture for probabilistic applications

L Leem, H Cho, J Bau, QA Jacobson… - … Design, Automation & …, 2010 - ieeexplore.ieee.org
There is a growing concern about the increasing vulnerability of future computing systems to
errors in the underlying hardware. Traditional redundancy techniques are expensive for …

Energy-efficient cache design using variable-strength error-correcting codes

AR Alameldeen, I Wagner, Z Chishti, W Wu… - ACM SIGARCH …, 2011 - dl.acm.org
Voltage scaling is one of the most effective mechanisms to improve microprocessors' energy
efficiency. However, processors cannot operate reliably below a minimum voltage, Vccmin …

Pseudo-sequence-based 2-D hierarchical coding structure for light-field image compression

L Li, Z Li, B Li, D Liu, H Li - IEEE Journal of Selected Topics in …, 2017 - ieeexplore.ieee.org
In this paper, we propose a pseudo-sequence-based two-dimensional (2-D) hierarchical
coding structure for light-field image compression. In the proposed scheme, we first …