Interconnect spacing is getting increasingly smaller in advanced technology nodes, which
adversely increases the capacitive coupling of adjacent interconnect wires. It makes …

In this paper, we propose the first wire density driven global routing that considers CMP
variation and timing. To enable CMP awareness during global routing, we propose a …

As VLSI technologies scale down, interconnect performance is greatly affected by crosstalk
noise due to the decreasing wire separation and increased wire aspect ratio, and crosstalk …

Gate sizing is a practical and a feasible crosstalk noise repair technique in the post route
design stage, especially for block level sea-of-gates designs. The difficulty in gate sizing for …

The sustained progress of VLSI technology has altered the landscape of routing which is a
major physical design stage. For timing driven routings, traditional approaches which …

Analyzing and evaluating various noise avoidance techniques such as driver sizing, wire
sizing, wire spacing and layer assignment. This paper presents an approach to solve the …

In ultra-deep submicron technology, crosstalk noise is so severe that crosstalk avoidance
merely in detailed routing is not adequate and it has to be considered in earlier design …

Crosstalk noise has become an important issue as technology scales down for timing and
signal integrity closure. Existing works to fix crosstalk noise are mostly done at the routing or …

This paper discusses challenges the designer faces in integrating entire system product
designs, containing tens or even hundreds of millions of logic gates, into single chip …

Signal integrity closure is one of the key challenges in deep submicron physical design. In
this paper, we propose a physical design methodology which includes signal integrity …