With the rapid advancement of CMOS technologies, nano-scale CMOS latches have
become increasingly sensitive to multiple-node upset (MNU) errors caused by radiations …

As ICs shrink into the nanometer range, they are increasingly subject to errors induced by
physical faults. Traditional hardening for error mitigation consumes too much area and …

This paper presents two novel low cost, double-and-triple-node-upset tolerant latch designs.
First, a novel low cost and double-node-upset (DNU) completely tolerant (LCDNUT) latch …

As the process feature size continues to scale down, the susceptibility of logic circuits to
radiation induced error has increased. This trend has led to the increase in sensitivity of …

In harsh radiation environments, nanoscale CMOS latches have become more and more
vulnerable to triple-node upsets (TNUs). This paper first proposes a latch design that can …

As technology scales down, soft errors, because of single event upsets (SEUs) that affect
multiple nodes (through multiple node charge sharing), become a serious concern in …

This work presents a single event double node upset (SEDNU) self-healing (DNUSH) latch
to meet the high-robustness requirement of the applications used in a harsh radiation …

In this paper we propose the novel Delta DICE latch that is tolerant to SNUs (Single Node
Upsets) and DNUs (Double Node Upsets). The latch comprises three DICE cells in a delta …

As technology size scales down toward lower two-digit nanometer dimensions, sensitivity of
CMOS circuits to radiation effects increases. Static random access memory cells (SRAMs) …

With the decrease of the device size, soft error induced by various particles becomes a
serious problem for advanced CMOS technologies. In this paper, we review the evolution of …