This review paper explores considerations for ultimate CMOS transistor scaling. Transistor
architectures such as extremely thin silicon-on-insulator and FinFET (and related …

Scaling of silicon transistors continue in the sub 100-nm regime amidst severe roadblocks.
Increased short-channel effects, rising leakage currents, severe process parameter …

The rapid cadence of metal-oxide semiconductor field-effect transistor (MOSFET) scaling, as
seen in the new 2003 International Technology Roadmap for Semiconductors ITRS), is …

Recently there has been tremendous progress made in the research of novel
nanotechnology for future nanoelectronic applications. In particular, several emerging …

To a large extent, scaling was not seriously challenged in the past. However, a closer look
reveals that early signs of scaling limits were seen in high-performance devices in recent …

In this Letter, we map for the first time the current distribution among the individual layers of
multilayer two-dimensional systems. Our findings suggest that in a multilayer MoS2 field …

Recent changes in CMOS device structures and materials motivated by impending atomistic
and quantum-mechanical limitations have profoundly influenced the nature of delay and …

4,746,630 4,789,560 4,882,291 4,897,700 4,903,344 4.959, 325 4,965,221 5,041,898
5,057.449 5,087,586 5,128.274 5,149,669 5,210,046 5,252.504 5,260,229 5,316,966 …

We report on measured radiation-induced soft error rates (SER) of memory and logic
devices built in a 22 nm high-k metal gate bulk Tri-Gate technology. Our results demonstrate …

(57) ABSTRACT A floating-body dynamic random access memory device may include a
semiconductor body having a top Surface and laterally opposite sidewalls formed on a …