System-on-Chip (SoC) complexity and the increasing costs of silicon motivate the breaking
of an SoC into smaller" chiplets." A chiplet-based SoC design process has the promise to …

In this paper, we propose a distributed routing algorithm for vertically partially connected
regular 2D topologies of different shapes and sizes (eg, 2D mesh, torus, ring). The …

Routing algorithms for NoCs were extensively studied in the last 12 years, and proposals for
algorithms targeting some cost function, as latency reduction or congestion avoidance …

The high-performance computing domain is enriching with the inclusion of networks-on-chip
(NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face the …

With the advent of deep sub-micron technology, fault-tolerant solutions are needed to keep
many-core chips operative. In NoCs, Logic Based Distributed Routing (LBDR) proved to be …

3D integrated circuits (3D ICs) using through-silicon vias (TSVs) allow to envision the
stacking of dies with different functions and technologies, using as an interconnect …

High-end MPSoC systems with built-in high-radix topologies achieve good performance
because of the improved connectivity and the reduced network diameter. In high-end …

Aggressive scaling of CMOS process technology allows the fabrication of highly integrated
chips such as NoC-based MPSoCs. However, fault probability increases when devices' size …

NoC-Based Dynamic Reconfigurable Systems (DRSs) implemented over FPGA devices
change their configuration at the run time by re-positioning or replacing the existing …

This paper presents a novel low-cost routing algorithm for regular (mesh) topology networks-
on-chip. While deterministic NoC routing algorithms such as XY routing are still widely used …