Experimental survey of FPGA-based monolithic switches and a novel queue balancer
This article studies small to medium-sized monolithic switches for FPGA implementation and
presents a novel switch design that achieves high algorithmic performance and FPGA …
presents a novel switch design that achieves high algorithmic performance and FPGA …
A low-latency Fair-Arbiter Architecture for Network-on-chip switches
J Luo, W Wu, Q Xing, M Xue, F Yu, Z Ma - Applied Sciences, 2022 - mdpi.com
As semiconductor technology evolves, computing platforms attempt to integrate hundreds of
processing cores and associated interconnects into a single chip. Network-on-chip (NoC) …
processing cores and associated interconnects into a single chip. Network-on-chip (NoC) …
Efficient deadlock avoidance for 2D mesh NoCs that use OQ or VOQ routers
P Papaphilippou, T Van Chu - IEEE Transactions on Computers, 2024 - ieeexplore.ieee.org
Network-on-chips (NoCs) are currently a widely used approach for achieving scalability of
multi-cores to many-cores, as well as for interconnecting other vital system-on-chip (SoC) …
multi-cores to many-cores, as well as for interconnecting other vital system-on-chip (SoC) …