A new approach to subquadratic space complexity parallel multipliers for extended binary fields

H Fan, MA Hasan - IEEE Transactions on Computers, 2007 - ieeexplore.ieee.org
Based on Toeplitz matrix-vector products and coordinate transformation techniques, we
present a new scheme for subquadratic space complexity parallel multiplication in GF (2 n) …

Systolic and Super-Systolic Multipliers for Finite Field Based on Irreducible Trinomials

PK Meher - IEEE Transactions on Circuits and Systems I …, 2008 - ieeexplore.ieee.org
Novel systolic and super-systolic architectures are presented for polynomial basis
multiplication over GF (2 m) based on irreducible trinomials. By suitable cut-set retiming, we …

Low-Latency, Low-Area, and Scalable Systolic-Like Modular Multipliers for Based on Irreducible All-One Polynomials

PK Meher, X Lou - IEEE Transactions on Circuits and Systems I …, 2016 - ieeexplore.ieee.org
In this paper, an efficient recursive formulation is suggested for systolic implementation of
canonical basis finite field multiplication over GF (2 m) based on irreducible AOP. We have …

Extended Number Theoretic Transform for Light-Weight Post-Quantum Cryptosystems in IoT

HG Joo, S Lee, DJ Shin - IEEE Internet of Things Journal, 2024 - ieeexplore.ieee.org
The primary computational complexity of the lattice-based post-quantum cryptosystems
(PQCs), aside from hashing, comes from the polynomial multiplication. Especially, the …

Low Power Semi-systolic Architectures for Polynomial-Basis Multiplication over GF(2 m ) Using Progressive Multiplier Reduction

A Ibrahim, F Gebali - Journal of Signal Processing Systems, 2016 - Springer
We present low area and low power semi-systolic array architectures for polynomial basis
multiplication over GF (2 m) using Progressive Multiplier Reduction Technique (PMR) …

Comb Architectures for Finite Field Multiplication in F (2^ m)

AH Namin, H Wu, M Ahmadi - IEEE Transactions on Computers, 2007 - ieeexplore.ieee.org
Two high-speed bit-serial word-parallel or comb-style finite field multipliers are proposed in
this paper. The first proposal utilizes a redundant representation for any binary field and the …

Software multiplication using Gaussian normal bases

R Dahab, D Hankerson, F Hu, M Long… - IEEE Transactions …, 2006 - ieeexplore.ieee.org
Fast algorithms for multiplication in finite fields are required for several cryptographic
applications, in particular for implementing elliptic curve operations over binary fields F/sub …

High-speed hybrid-double multiplication architectures using new serial-out bit-level mastrovito multipliers

EAH Abdulrahman… - IEEE Transactions on …, 2015 - ieeexplore.ieee.org
The Serial-out bit-level multiplication scheme is characterized by an important latency
feature. It has an ability to sequentially generate an output bit of the multiplication result in …

Low space-complexity and low power semi-systolic multiplier architectures over GF (2m) based on irreducible trinomial

F Gebali, A Ibrahim - Microprocessors and Microsystems, 2016 - Elsevier
This paper proposes a three bit-serial and digit-serial semi-systolic GF (2 m) multipliers
using Progressive Product Reduction (PPR) technique. These architectures are obtained by …

Low-complexity finite field multiplier using irreducible trinomials

CW Chiou, LC Lin, FH Chou, SF Shu - Electronics Letters, 2003 - search.proquest.com
A low-complexity array multiplier for GF (2^ sup m^) fields with an irreducible trinomial X^
sup m^+ X^ sup n^+ 1 is presented. The space complexity of the proposed multiplier is …