[HTML][HTML] InP photonic integrated multi-layer neural networks: Architecture and performance analysis

B Shi, N Calabretta, R Stabile - APL Photonics, 2022 - pubs.aip.org
We demonstrate the use of a wavelength converter, based on cross-gain modulation in a
semiconductor optical amplifier (SOA), as a nonlinear function co-integrated within an all …

6GS/s 8-channel CIC SAR TI-ADC with neural network calibration

E Ware, J Correll, S Lee, M Flynn - ESSCIRC 2022-IEEE 48th …, 2022 - ieeexplore.ieee.org
In this paper we introduce an area efficient time-interleaved charge-injection-cell SAR ADC.
The prototype TI-ADC interleaves 8 CIC SAR channels for a sampling rate of 6Gs/s and a …

Parallel photonic convolutional processing on-chip with cross-connect architecture and cyclic AWGs

B Shi, N Calabretta, R Stabile - IEEE Journal of Selected Topics …, 2022 - ieeexplore.ieee.org
Convolutional neural network (CNN) is one of the best neural network structures for solving
classification problems. The convolutional processing of the network dominates processing …

An 8-bit 10-GHz 21-mW time-interleaved SAR ADC with grouped DAC capacitors and dual-path bootstrapped switch

E Swindlehurst, H Jensen, A Petrie… - IEEE Journal of Solid …, 2021 - ieeexplore.ieee.org
An 8-bit 10-GHz 8× time-interleaved successive-approximation-register (SAR) analog-to-
digital converter (ADC) incorporates an aggressively scaled digital-to-analog converter …

A 0.2-V 10-bit 5-kHz SAR ADC with dynamic bulk biasing and ultra-low-supply-voltage comparator

A Petrie, Y Song, W Kinnison, Y Qu… - … on Circuits and …, 2023 - ieeexplore.ieee.org
This paper describes a 10-bit 5-kHz SAR ADC under an ultra-low-supply-voltage of 0.2 V for
low-power applications. To tolerate the severe variations in the subthreshold regime, a novel …

General approach to the calibration of innovative MFP multichannel digitizers

F Centurelli, P Monsurrò, A Trifiletti… - IEEE Transactions …, 2022 - ieeexplore.ieee.org
Innovative digitizers exploiting mixing, filtering, and processing (MFP) operations can grant
ultrahigh bandwidth and sampling rate. Their operation combines analog processing stages …

10-Bit 5 MS/s Successive Approximation Register Analog-to-Digital Converter with a Phase-Locked Loop and Modified Bootstrapped Switch for a BLDC Motor Drive

GM Sung, CC Huang, X Xiao, SY Hsu - Electronics, 2022 - mdpi.com
In this paper, we present a successive approximation register (SAR) analog-to-digital
converter (ADC) with a charge-pump (CP) phase-locked loop (PLL) and a bootstrapped …

On automating finger-cap array synthesis with optimal parasitic matching for custom SAR ADC

CY Chiang, CL Hu, MPH Lin, YS Chung… - Proceedings of the 28th …, 2023 - dl.acm.org
Due to its excellent power efficiency, the successive-approximation-register (SAR) analog-to-
digital converter (ADC) is an attractive design choice for low-power ADC implements. In …

[图书][B] Multi-Gigahertz Nyquist Analog-to-Digital Converters: Architecture and Circuit Innovations in Deep-Scaled CMOS and FinFET Technologies

This book proposes innovative circuit, architecture, and system solutions in deep-scaled
CMOS and FinFET technologies, which address the challenges in maximizing the accuracy …

Bootstrapped switch with improved linearity based on a negative-voltage bootstrapped capacitor

C Wei, R Wei, M He - IEICE Electronics Express, 2021 - jstage.jst.go.jp
This study introduces a new bootstrapped switch for improving sampling linearity. In this
technology, the introduction of a negative-voltage bootstrap capacitor reduces the parasitic …