随着集成电路规模越来越大, 设计变得越来越复杂. 为了有效地提升设计生产率,
芯片敏捷设计受到越来越广泛的重视. 在芯片RTL-to-GDSII 设计流程中, 敏捷设计方法需要广泛 …

Timing closure is a critical but effort-taking task in VLSI designs. In placement stage, a fast
and accurate net delay estimator is highly desirable to guide the timing optimization prior to …

Timing estimation prior to routing is of vital importance for optimization at placement stage
and timing closure. Existing wire-or net-oriented learning-based methods limits the accuracy …

Timing prediction and optimization are challenging in design stages prior to detailed routing
(DR) due to the unavailability of routing information. Inaccurate timing prediction wastes …

Accurate wire timing estimation has become a bottleneck in timing optimization since it
needs a long turn-around time using a sign-off timer. The gate timing can be calculated …

In this work, we introduce GraPhSyM, a Graph Attention Network (GATv2) model for fast and
accurate estimation of post-physical synthesis circuit delay and area metrics from pre …

Due to the unavailability of routing information in design stages prior to detailed routing
(DR), the tasks of timing prediction and optimization pose major challenges. Inaccurate …

With process technology scaling, accurate gate-level timing analysis becomes even more
challenging. Highly resistive on-chip interconnects have an ever-increasing impact on …

Timing mismatch between different stages of physical design poses great challenges for
circuit optimization to achieve the desired performance, power, and area (PPA) tradeoff. The …

In the advanced technology, the accuracy of cell and wire delay modeling are the key
metrics for timing analysis. However, when the supply voltage decreases to the near …