Processors and operating systems (OSes) support multiple memory page sizes. Superpages
increase Translation Lookaside Buffer (TLB) hits, while small pages provide fine-grained …

Address translation is fundamental to processor performance. Prior work focused on
reducing Translation Lookaside Buffer (TLB) misses to improve performance and energy …

Current cloud data centers are fully virtualized for service consolidation and power/energy
reduction. Although virtualization could reduce the real-time power consumption and overall …

To improve system performance, operating systems (OSes) often undertake activities that
require modification of virtual-to-physical address translations. For example, the OS may …

Virtual memory, specifically paging, is undergoing significant innovation due to being
challenged by new demands from modern workloads. Recent work has demonstrated an …

Translation Lookaside Buffers (TLBs) play a critical role in hardware-supported memory
virtualization. To speed up address translation and reduce costly page table walks, TLBs …

Associative access is widely used in fundamental microarchitectural components, such as
caches and TLBs. However, associative (or content addressable) memories (CAMs) have …

Conventional virtual memory (VM) frameworks enable a virtual address to flexibly map to
any physical address. This flexibility necessitates large data structures to store virtual-to …

Virtual memory is a critical abstraction in modern computer systems. Its common model,
paging, is currently seeing considerable innovation, yet its implementations continue to be …

Virtual caches have potentially lower access latency and energy consumption than physical
caches because they do not consult the TLB prior to cache access. However, they have not …