Massively parallel processing system using two data paths: one connecting router circuit to the interconnect network and the other connecting router circuit to I/O …

RE Kessler, SM Oberlin, SL Scott - US Patent 5,864,738, 1999 - Google Patents
[57] ABSTRACT A system and method of transferring information between a peripheral
device and an MPP system having an interconnect network and a plurality of processing …

Hybrid hypercube/torus architecture

RS Passint, G Thorson, MB Galles - US Patent 6,230,252, 2001 - Google Patents
A scalable multiprocessor system includes processing element nodes. A scalable
interconnect network includes physical communication links interconnecting the processing …

Router table lookup mechanism

RS Passint, MB Galles, G Thorson - US Patent 5,970,232, 1999 - Google Patents
A multiprocessor computer system includes processing element nodes interconnected by
physical communication links in a n-dimensional topology, which includes at least two …

Age-based network arbitration system and method

RS Passint, GM Thorson, T Stremcha - US Patent 6,674,720, 2004 - Google Patents
In a multiprocessor system having a plurality of nodes connected to a network, wherein
communication between the plurality of nodes is in the form of packets, a system and …

Virtual maintenance network in multiprocessing system having a non-flow controlled virtual maintenance channel

GM Thorson - US Patent 6,055,618, 2000 - Google Patents
Multiprocessor computer Systems comprise a number of processing element nodes
connected together by an inter connect network. The interconnect network transmits pack ets …

Using external registers to extend memory reference capabilities of a microprocessor

RE Kessler, SM Oberlin, SL Scott, EC Fromm - US Patent 5,835,925, 1998 - Google Patents
57 ABSTRACT A System and method of accessing a memory location within a System
having a processor and a plurality of memory locations Separate from the processor. The …

Multistream processing memory-and barrier-synchronization method and apparatus

SL Scott, GJ Faanes, B Stephenson… - US Patent …, 2008 - Google Patents
A method and apparatus to provide specifiable ordering between and among vector and
scalar operations within a single streaming processor (SSP) via a local synchronization …

System and method for fast barrier synchronization

SL Scott, RE Kessler - US Patent 6,216,174, 2001 - Google Patents
$3.5'3. ES et al........................... 33. Improved method and apparatus for facilitating fast barrier
4811214 3/1989 Nicket at... 364f200 Synchronization in a parallel-processing System. A …

Relaxed memory consistency model

SL Scott, GJ Faanes, B Stephenson… - US Patent …, 2012 - Google Patents
4,989,131 A 1, 1991 SR provides synchronization even outside a single MSP system
5,008,882 A 4, 1991 Peterson et al. is described. Advantageously, the pipeline or queue of …

Decoupled scalar/vector computer architecture system and method

GJ Faanes, SL Scott, EP Lundberg… - US Patent …, 2008 - Google Patents
In a computer system having a scalar processing unit and a vector processing unit, wherein
the vector processing unit includes a vector dispatch unit, a system and method of …